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Intel(R) Entry Server Board SE7230CA1-E
Technical Product Specification
D59801-001
Revision 1.0 April 2006 Enterprise Platforms and Services Division
Revision History
Intel(R) Entry Server Board SE7230CA1-E TPS
Revision History
Date April 2006 May 2006 Revision Number 0.5 1.0 Modifications Release subject to change. Update bios.
Disclaimers
Information in this document is provided in connection with Intel(R) products. No license, express, implied, by estoppel, or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. The Intel(R) Entry Server Board SE7230CA1-E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Intel, Pentium(R), Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright (c) Intel Corporation 2006.
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Table of Contents
Table of Contents
1. Introduction .......................................................................................................................... 1 1.1 1.2 2. 3. 2.1 3.1 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 4. 4.1 4.1.1 4.1.2 4.1.3 4.1.4
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Section Outline ........................................................................................................ 1 Server Board Use Disclaimer .................................................................................. 1 Intel(R) Entry Server Board SE7230CA1-E Feature Set............................................ 2 Processor Sub-System ............................................................................................ 7 Processor Voltage Regulator Down (VRD).............................................................. 8 Reset Configuration Logic ....................................................................................... 8 Processor Support ................................................................................................... 8 Intel(R) E7230 Chipset................................................................................................ 9 Intel(R) E7230 Chipset MCH: Memory Control Hub .................................................. 9 I/O Controller Hub.................................................................................................. 12 Memory Sub-System ............................................................................................. 14 Memory Configuration ........................................................................................... 14 Memory DIMM Support.......................................................................................... 16 I/O Sub-System ..................................................................................................... 16 PCI Subsystem ...................................................................................................... 16 Interrupt Routing .................................................................................................... 18 PCI Error Handling................................................................................................. 19 Video Support ........................................................................................................ 22 Network Interface Controller (NIC) ........................................................................ 22 Super I/O Chip ....................................................................................................... 23 BIOS Flash ............................................................................................................ 24 System Health Support.......................................................................................... 25 Replacing the Back-Up Battery.............................................................................. 25 BIOS Setup Utility .................................................................................................. 26 Localization............................................................................................................ 26 Configuration Reset ............................................................................................... 26 Keyboard Commands ............................................................................................ 26 Entering BIOS Setup ............................................................................................. 27
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Server Board Overview ........................................................................................................ 2 Functional Architecture ....................................................................................................... 6
System BIOS ....................................................................................................................... 26
Table of Contents
Intel(R) Entry Server Board SE7230CA1-E TPS
4.1.5 4.2 4.2.1 4.2.2 4.3 4.3.1 4.4 4.4.1 4.4.2 4.4.3 4.4.4 5. 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.3.1 5.4 5.5 5.5.1 5.5.2 5.5.3 6. 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.2.1 6.2.2 6.2.3 6.2.4
Operation ...............................................................................................................36 Flash Memory Update Utility.................................................................................. 37 BIOS Update.......................................................................................................... 37 O/S Present Flash Utility........................................................................................ 38 DMI/SMBIOS Support............................................................................................ 38 DMI/SMBIOS Write Tool ........................................................................................ 38 Operating System Boot, Sleep, and Wake ............................................................ 38 Boot Device Selection............................................................................................ 38 Operating System Support .................................................................................... 38 Front Control Panel Support .................................................................................. 40 Sleep and Wake Support....................................................................................... 40 Console Redirection .............................................................................................. 41 Serial Configuration Settings ................................................................................. 41 Keystroke Mappings .............................................................................................. 41 Limitations.............................................................................................................. 42 Intel(R) Active Management Technology (AMT) ....................................................... 42 Wired For Management (WFM) ............................................................................. 44 PXE BIOS Support ................................................................................................ 44 System Management BIOS (SMBIOS) .................................................................. 44 Security.................................................................................................................. 44 Operating Model .................................................................................................... 44 Password Protection.............................................................................................. 45 Password Clear Jumper ........................................................................................ 45 Error Handling and Logging................................................................................... 46 Error Sources and Types....................................................................................... 46 Error Logging via SMI Handler .............................................................................. 47 SMBIOS Type 15 ................................................................................................... 47 Logging Format Conventions................................................................................. 47 Error Messages and Error Codes .......................................................................... 49 Diagnostic LEDs .................................................................................................... 49 POST Code Checkpoints....................................................................................... 50 POST Error Messages and Handling .................................................................... 53 POST Error Beep Codes ....................................................................................... 54
Server Management ........................................................................................................... 41
Error Reporting and Handling ........................................................................................... 46
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6.2.5 7. 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.6 7.6.1 7.6.2 7.6.3 7.7 7.7.1 8. 9. 8.1 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.3.1 9.3.2 9.3.3 9.4 9.5 9.6
POST Error Pause Option ..................................................................................... 54 Power Connectors ................................................................................................. 55 I2C Header ............................................................................................................. 55 Front Panel Connector........................................................................................... 56 I/O Connectors....................................................................................................... 56 VGA Connector...................................................................................................... 56 NIC Connectors ..................................................................................................... 57 SATA Connectors .................................................................................................. 57 Serial Port Connectors........................................................................................... 57 USB Connector...................................................................................................... 58 Fan Headers .......................................................................................................... 59 Miscellaneous Headers and Connectors ............................................................... 59 Chassis Intrusion Header ...................................................................................... 59 Back Panel I/O Connectors ................................................................................... 59 POST Code LEDs.................................................................................................. 60 Jumper Blocks ....................................................................................................... 60 Clear CMOS and System Maintenance Mode Jumpers ........................................ 60 Mean Time Between Failures (MTBF) Test Results .............................................. 61 Power Budget ........................................................................................................ 62 Product Regulatory Compliance ............................................................................ 62 Product Safety Compliance ................................................................................... 62 Product EMC Compliance - Class A Compliance ................................................. 63 Certifications / Registrations / Declarations ........................................................... 63 Product Regulatory Compliance Markings ............................................................ 64 Electromagnetic Compatibility Notices .................................................................. 64 Industry Canada (ICES-003) ................................................................................. 64 Europe (CE Declaration of Conformity) ................................................................. 65 Australia / New Zealand......................................................................................... 65 Restriction of Hazardous Substances (RoHS)....................................................... 65 Calculated Mean Time Between Failures (MTBF) ................................................. 65 Mechanical Specifications ..................................................................................... 65
Connectors and Jumper Blocks ....................................................................................... 55
Absolute Maximum Ratings .............................................................................................. 61 Design and Environmental Specifications....................................................................... 62
10. Hardware Monitoring ......................................................................................................... 67
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10.1 10.1.1 10.2
Monitored Components..........................................................................................67 Fan Speed Control................................................................................................. 67 Chassis Intrusion ................................................................................................... 68
Glossary..................................................................................................................................... 69 References................................................................................................................................. 72
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List of Figures
List of Figures
Figure 1. Intel(R) Entry Server Board SE7230CA1-E Layout.......................................................... 4 Figure 2. Intel(R) Entry Server Board SE7230CA1-E Block Diagram ............................................. 6 Figure 3. Memory Bank Label Definition..................................................................................... 15 Figure 4. Interrupt Routing Diagram ........................................................................................... 20 Figure 5. Intel(R) ICH7R Interrupt Routing Diagram ..................................................................... 21 Figure 6. Location of Diagnostic LEDs on Server Board ............................................................ 50 Figure 7. Back Panel I/O Connections (not to scale) .................................................................. 59 Figure 8. Intel(R) Entry Server Board SE7230CA1-E Mechanical Drawing .................................. 66 Figure 9. Fan Speed Control Block Diagram .............................................................................. 67
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List of Tables
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List of Tables
Table 1. Server Board Layout Reference ..................................................................................... 5 Table 2. Processor Support Matrix ............................................................................................... 9 Table 3. Supported DDR2 Modules ............................................................................................ 11 Table 4. Segment B Configuration.............................................................................................. 11 Table 5. Segment B Arbitration Connections.............................................................................. 11 Table 6. Memory Bank Labels and DIMM Population Order....................................................... 15 Table 7. Characteristics of Dual/Single Channel Configuration with or without Dynamic Mode . 16 Table 8. PCI Bus Segment Characteristics................................................................................. 17 Table 9. Segment A Configuration IDs ....................................................................................... 17 Table 10. Segment A Arbitration Connections............................................................................ 17 Table 11. PCI Interrupt Routing/Sharing..................................................................................... 18 Table 12. Interrupt Definitions..................................................................................................... 19 Table 13. Video Modes ............................................................................................................... 22 Table 14. Intel(R) 82573E (NIC 1 and NIC 2) ............................................................................... 23 Table 15. Serial A Header Pin-out .............................................................................................. 24 Table 16. Serial B Header Pin-out .............................................................................................. 24 Table 17. BIOS Setup Keyboard Command Bar Options ........................................................... 26 Table 18. BIOS Setup, Main Menu Options ................................................................................ 28 Table 19. BIOS Setup, Additional System Information Sub-menu Selections ............................ 28 Table 20. BIOS Setup, Advanced Menu Options........................................................................ 29 Table 21. BIOS Setup, Advanced Menu, Boot Configuration Sub-menu Selections .................. 29 Table 22. BIOS Setup, Advanced Menu, Peripheral Configuration Sub-menu........................... 30 Table 23. BIOS Setup, Advanced Menu, Drive Configuration Menu Options ............................. 30 Table 24. BIOS Setup, Advanced Menu, Event Log Configuration Sub-menu Selections ......... 31 Table 25. BIOS Setup, Advanced Menu, Video Configuration Sub-menu Selections ................ 31 Table 26. BIOS Setup, Advanced Menu, Hardware Monitoring Sub-menu Selections............... 32 Table 27. BIOS Setup, Advanced Menu, Chipset Configuration Sub-menu Selections ............. 32 Table 28. BIOS Setup, Advanced Menu, Chipset Configuration, Memory Configuration Submenu Selections................................................................................................................... 33 Table 29. BIOS Setup, Advanced Menu, Chipset Configuration, PCI Express* Configuration Sub-menu Selections ........................................................................................................... 33 Table 30. BIOS Setup, Advanced Menu, Management Configuration Sub-menu Selections..... 33
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Table 31. BIOS Setup, Advanced Menu, USB Mass Storage Device Configuration Sub-menu Selections............................................................................................................................. 34 Table 32. BIOS Setup, Security Menu Options........................................................................... 34 Table 33. BIOS Setup, Power Menu Selections ......................................................................... 34 Table 34. BIOS Setup, Boot Menu Selections ............................................................................ 35 Table 35. BIOS Setup, Exit Menu Selections ............................................................................. 35 Table 36. BIOS Setup Page Layout............................................................................................ 36 Table 37. Console Redirection Escape Sequences for Headless Operation.............................. 42 Table 38. Function List................................................................................................................ 44 Table 39. Security Features Operating Model ............................................................................ 45 Table 40. Event List .................................................................................................................... 46 Table 41. Logging Format Conventions...................................................................................... 48 Table 42. Event Type Definition Table........................................................................................ 48 Table 43. POST Progress Code LED Example .......................................................................... 50 Table 44. POST Code Checkpoints............................................................................................ 50 Table 45. POST Error Messages and Handling.......................................................................... 54 Table 46. POST Error Beep Codes ............................................................................................ 54 Table 47. Power Connector Pin-out (J3K1) ................................................................................ 55 Table 48. HSBP Header Pin-out (J1C1) ..................................................................................... 55 Table 49. Front Panel 14-pin Header Pin-out (J4k2) .................................................................. 56 Table 50. VGA Connector Pin-out (J3A1)................................................................................... 56 Table 51. NIC1-Intel(R) 82573E (10/100/1000) Connector Pin-out (JA5A1) ................................ 57 Table 52. NIC2- Intel(R) 82541PI (10/100/1000) Connector Pin-out (JA4A1) .............................. 57 Table 53. SATA Connector Pin-out (J5C1, J5C2) ...................................................................... 57 Table 54. External DB9 Serial A Port Pin-out (J3A1).................................................................. 58 Table 55. Internal 9-pin Serial B Port Pin-out (J1C2).................................................................. 58 Table 56. USB Connectors Pin-out (JA5A1)............................................................................... 58 Table 57. Optional USB Connection Header Pin-out (J9F2) ...................................................... 58 Table 58. Four-pin Fan Headers Pin-out (J3K2, J4K1).............................................................. 59 Table 59. Intrusion Cable Connector (J3B2) Pin-out ................................................................. 59 Table 60. System Maintenance Mode (J1A3)............................................................................. 60 Table 61. Clear CMOS Jumper Options (J3B2).......................................................................... 60 Table 62. Absolute Maximum Ratings ........................................................................................ 61 Table 63. The Board Power Budget............................................................................................ 62 Table 64. Product Certification Markings .................................................................................... 64
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Intel(R) Entry Server Board SE7230CA1-E TPS
Table 65. MTBF Data..................................................................................................................65 Table 66. Monitored Components............................................................................................... 67
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Introduction
1.
Introduction
This Intel(R) Entry Server Board SE7230CA1-E Technical Product Specification (TPS) provides a high-level technical description for the Intel(R) Entry Server Board SE7230CA1-E. It details the architecture and feature set for all functional sub-systems that make up the server board.
1.1
Section Outline
Section 1 - Introduction Section 2 - Server Board Overview Section 3 - Functional Architecture Section 4 - System BIOS Section 5 - Platform Management Architecture Section 6 - Error Reporting and Handling Section 7 - Connectors and Jumper Blocks Section 8 - Absolute Maximum Ratings Section 9 - Design and Environmental Specifications Section 10 - Hardware Monitoring Appendix A - Integration and Usage Tips Glossary Reference Documents
This document is divided into the following chapters:
1.2
Server Board Use Disclaimer
Intel(R) server boards contain a number of high-density VLSI* and power delivery components that need adequate airflow to cool. Intel's own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.
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Server Board Overview
Intel(R) Entry Server Board SE7230CA1-E TPS
2.
Server Board Overview
The Intel(R) Entry Server Board SE7230CA1-E is a monolithic printed circuit board with features that support the UP server high-density (1U) market.
2.1
Intel(R) Entry Server Board SE7230CA1-E Feature Set
Processor and Front Side Bus (FSB) support - Supports Pentium(R) 4 processor Extreme Edition, Pentium(R) processor Extreme Edition, Pentium(R) D, Pentium(R) 4 and Celeron(R) D processors in the Intel(R) 775-pin PLGA package - Supports Intel(R) Dual Core Architecture - Supports Hyper-Threading Technology - Supports Intel(R) Extended Memory System 64 Technology (Intel(R) EM64T) Intel(R) E7230 Chipset components - Intel(R) E7230 MCH Memory Controller Hub - Intel(R) ICH7R I/O Controller - 12-deep In-order Queue Memory System - Four DIMM sockets supporting 533/667MHz DDR2 DIMMs - Data bandwidth per channel of 4.2GB/s or 8.4GB/s in dual channel when using DDR2 667MHz - Support for up to two DDR2 channels for a total of four DIMMs (two DIMMs / channel) providing up to 8 MB max memory capacity. - Support for 512-MB, 1-GB and 2-GB DDR2 DIMMs I/O Subsystem Board I/O Subsystem (Two independent PCI buses): - Segment A: One embedded Intel(R) Gigabit Ethernet Controller 10/100/1000 82541PI (Supports PCI Specification, Rev 2.3) - Segment B: One x1 PCI Express* resource implemented as an embedded Intel(R) 10/100/1000 82573E Gigabit Ethernet Controller Serial ATA host controller Two independent SATA ports support data transfer rates up to 1.5 Gb/s (150MB/s) per port Universal Serial Bus 2.0 (USB) Two external USB ports with an additional internal header providing two optional USB ports for front panel support. - Supports wake-up from sleeping states S1-S4 (S3 not supported) - Supports Legacy Keyboard/Mouse connections when using PS2-USB dongle LPC (Low Pin Count) bus segment with one embedded device
The Intel(R) Entry Server Board SE7230CA1-E supports the following feature set:
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Server Board Overview
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Super I/O controller chips providing all PC-compatible I/O (floppy, serial, keyboard, mouse, two serial com port ) and integrated hardware monitoring - LC Super I/O = SMsC* LP47M182NR Standard Intel(R) 14-pin SSI front panel 2x9 power connectors Fan Support - Two general purpose 4-pin fans Intel(R) Light-guided Diagnostic LEDs to display POST code indicators during boot
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Server Board Overview
Intel(R) Entry Server Board SE7230CA1-E TPS
The following figure shows the board layout of the Intel(R) Entry Server Board SE7230CA1-E. Each connector and major component is identified by letter and is identified in Table 1.
Figure 1. Intel(R) Entry Server Board SE7230CA1-E Layout
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Table 1. Server Board Layout Reference
Ref A B C D E F G H I J K L M N O P Post LEDs BIOS recovery jumper BIOS Flash(FWH) ATI* ES1000 video controller Chassis intrusion header Battery I2C Connector Serial B header SMSC* LPC47M182 SIO Memory Slot DIMM 1A Memory Slot DIMM 2A Memory Slot DIMM 1B Memory Slot DIMM 2B 2 x 9 Power connector NIC1 RJ-45 and USB 1 and 2 connector NIC2 RJ-45 connector Description Ref Q R S T U V W X Y Z AA BB CC DD EE FF Description NIC1 SPI Flash Intel(R) 82541PI LAN Controller NIC2 SPI EEPROM Intel(R) AMT firmware update jumper Intel(R) 82573E LAN Controller USB 3 and 4 header Clear CMOS jumper SATA port 2 SATA port 1 Intel(R) 82802 ICH7R Intel(R) E7230 MCH 775-Land (LGA) CPU Socket System Fan 1 (4-pin) System Fan 2 (4-pin) 2 x 7 Front Panel header Hardware Management Controller
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Functional Architecture
Intel(R) Entry Server Board SE7230CA1-E TPS
3.
Functional Architecture
This section provides a high-level description of the functionality associated with the architectural blocks that make up the Intel(R) Entry Server Board SE7230CA1-E.
Figure 2. Intel(R) Entry Server Board SE7230CA1-E Block Diagram
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3.1
Processor Sub-System
Pentium(R) 4 processor Extreme Edition in the 775-land package Pentium(R) processor Extreme Edition in the 775-land package Pentium(R) D processors in the 775-land package Pentium(R) 4 processors in the 775-land package Celeron(R) D processors in the 775-land package
The Intel(R) Entry Server Board SE7230CA1-E supports the following:
The 775-land package is a follow-on to Pentium(R) 4 and Celeron(R) processors in the 478-pin package with enhancements to the Intel NetBurst(R) micro-architecture, including but not limited to the following: Dual Core Architecture Hyper-Threading Technology Intel(R) EM64T Pentium(R) 4 processor Extreme Edition Pentium(R) processor Extreme Edition Pentium(R) D processor Pentium(R) 4 processor Celeron(R) D processor The processors built on 90-nm and 65-nm process technology in the 775-land package utilize Flip-Chip Land Grid Array (FC-LGA4) package technology, and plug into a 775-land LGA socket, referred to as the Intel(R) LGA775 socket. The processors are as follows: Pentium(R) 4 processor Extreme Edition, Pentium(R) processor Extreme Edition Pentium(R) D processor Pentium(R) 4 Processor Celeron(R) D Processor The above processors in the 775-land package, like their predecessors in the 478-pin package, are based on the same Pentium(R) 4 micro-architecture. They maintain compatibility with 32-bit software written for the IA-32 instruction set, while supporting 64-bit native mode operation when coupled with supported 64-bit operating systems and applications. The Celeron(R) processor does not come in a dual-core configuration, or support HyperThreading Technology or Intel(R) EM64T.
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3.1.1
Processor Voltage Regulator Down (VRD)
The Intel(R) Entry Server Board SE7230CA1-E has a VRD (Voltage Regulator Down) to support one processor. It is compliant with the VRM 10.1 DC-DC Converter Design Guide Line and provides a maximum of 120A, which is capable of supporting the requirements for the following processors: Pentium(R) 4 processor Extreme Edition Pentium(R) processor Extreme Edition Pentium(R) D Processor Pentium(R) 4 Processor Celeron(R) D Processor The board hardware monitors the processor VTTEN (Output enable for VTT) pin before turning on the VRD. If the VTTEN pin of the processors is not identical, the Power On Logic will not turn on the VRD.
3.1.2
Reset Configuration Logic
The BIOS determines the processor stepping, cache size, etc., through the CPUID instruction. The requirement is: Processor run at a fixed speed, but BIOS can program it to operate at a lower or higher speed. The processor information is read at every system power-on. Note: The processor speed is the processor power-on reset default value. No manual processor speed setting options exist either in the form of a BIOS setup option or jumpers.
3.1.3
Processor Support
The Intel(R) Entry Server Board SE7230CA1-E supports one processor in the Intel(R) LGA775 package. The support circuitry on the server board consists of the following: Intel(R) LGA775 processor socket supporting: - Pentium(R) D Processor with 800MHz system bus - Pentium(R) 4 Processor with 800MHz system bus - Pentium(R) 4 processor Extreme Edition with 1066 MHz system bus Processor host bus AGTL+ support circuitry
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Table 2. Processor Support Matrix
Processor Family Pentium(R) 4 processor Extreme Edition Pentium(R) D processor Pentium(R) 4 processor Celeron(R) D processor Package Type Intel(R) LGA775 Intel(R) LGA775 Intel(R) LGA775 Intel(R) LGA775 Frequency 3.73GHz 2.8 - 3.6GHz 3.2 - 3.8 GHz 2.26 - 3.2 GHz Cache Size 2MB L2 2 x 1MB or 2x 2MB L2 1MB or 2MB L2 256K L2 Front Side Bus 1066MHz 800MHz 800MHz 533MHz
Note: For a complete list of all supported processors, please visit the Intel(R) Entry Server Board SE7230CA1-E support site located at the following URL:
http://support.intel.com/support/motherboards/server/ In addition to the circuitry described above, the processor subsystem contains the following: Reset configuration logic Server management registers and sensors
3.2
Intel(R) E7230 Chipset
The Intel(R) Entry Server Board SE7230CA1-E is designed around the Intel(R) E7230 Chipset. The chipset provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI Express*).
3.2.1
Intel(R) E7230 Chipset MCH: Memory Control Hub
The MCH accepts access requests from the host (processor) bus and directs those accesses to memory or to one of the PCI buses. The MCH monitors the host bus, examining addresses for each request. Accesses may be directed to the following: A memory request queue for subsequent forwarding to the memory sub-system An outbound request queue for subsequent forwarding to one of the PCI buses The MCH also accepts inbound requests from the Intel(R) ICH7R. The MCH is responsible for generating the appropriate controls to control data transfer to and from memory.
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Functional Architecture
Intel(R) Entry Server Board SE7230CA1-E TPS
The MCH is a 1210-ball FC-BGA device and uses the proven components of the following previous generations: Pentium(R) 4 processor Extreme Edition Pentium(R) processor Extreme Edition Pentium(R) D Processor Pentium(R) 4 Processor bus interface unit Hub interface unit DDR2 memory interface unit The MCH also increases the main memory interface bandwidth and maximum memory configuration with a 72-bit wide memory interface. The MCH integrates the following main functions: An integrated high performance main memory subsystem A DMI which provides an interface to the Intel(R) ICH7R Other features provided by the MCH include the following: Full support of ECC on the processor bus Full support of Intel(R) x4 Single Device Data Correction on the memory interface with x4 DIMMs Twelve deep in-order queue, two deep defer queue Full support of un-buffered DDR2 ECC DIMMs Support for 1 GB and 2 GB DDR2 memory modules Memory scrubbing 3.2.1.1 MCH Memory Sub-System Overview
The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of DDR2 memory using 2 GB DIMMs. This configuration needs external registers for buffering the memory address and control signals. The four chip selects are registered inside the MCH and need no external registers for chip selects. The memory interface runs at 533/667MT/s. The memory interface supports a 72-bit wide memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 512-MB, 1-GB, and 2-GB DRAM densities. The DDR DIMM interface supports memory scrubbing, singlebit error correction, and multiple-bit error detection and Intel(R) x4 Single Device Data Correction with x4 DIMMs. The DDR2 interface supports up to 8 GB of main memory and supports single- and doubledensity DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the DDR2 DIMM technology supported.
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Table 3. Supported DDR2 Modules
DDR2-533/667 Un-buffered SDRAM Module Matrix SDRAM SDRAM # SDRAM # Address bits Density Organization Devices/rows/Banks rows/Banks/column 256Mbit 32M x 8 18 / 2 / 4 13 / 2 / 10 512Mbit 512Mbit 1Gbit 2GB 64M x 8 64M x 8 128M x 8 128M x 8 9/1/4 18 / 2 / 4 9/1/8 18 / 2 / 8 14 / 2 / 10 14 / 2 / 10 14 / 4 / 10 14 / 8 / 10
DIMM Capacity 512 MB 512 MB 1 GB 1 GB 2 GB
DIMM Organization 64M x 72 64M x 72 128M x 72 128M x 72 256M x 72
3.2.1.2 3.2.1.2.1
PCI Express* x1 PCI Express* Subsystem
The Intel(R) ICH7R supports two x 1 PCI Express* buses. Only one is used to support the Intel(R) 82573-Gigabit Ethernet Controller. One 32-bit PCI bus segment is directed through the Intel(R) ICH7R Interface A. This PCI Segment B has an embedded device, the Intel(R) 82541PI LAN (NIC2). Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD [31:16], which acts as a chip select on the PCI bus segment in configuration cycles. This determines a unique PCI device ID value for use in configuration cycles. The following table shows the bit to which each IDSEL signal is attached for P32-B devices and the corresponding device description:
Table 4. Segment B Configuration
IDSEL Value 21 Intel(R) 82541PI LAN (NIC2) Device
PCI Segment B supports one PCI master. All PCI masters must arbitrate for PCI access using resources supplied by the Intel(R) ICH7R. The host bridge PCI interface arbitration lines REQx* and GNTx* are internal to the Intel(R) ICH7R. The following table defines the arbitration connections:
Table 5. Segment B Arbitration Connections
Server board Signals PCIX REQ_N5/GNT_N5 Device Intel(R) 82541PI LAN (NIC2)
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3.2.2
3.2.2.1
I/O Controller Hub
Intel(R) ICH7R: I/O Controller Hub 7R
The Intel(R) ICH7R controller has several components. It provides the interface for a 32-bit/33-MHz PCI bus. The Intel(R) ICH7R can be both a master and a target on that PCI bus and includes a USB 2.0 controller and an IDE controller. The ICH7R controller is also responsible for much of the power management functions, with ACPI control registers built in. It also provides a number of GPIO pins and has the LPC bus to support low-speed Legacy I/O. The MCH and Intel(R) ICH7R chips provide the pathway between the processor and the I/O systems. The MCH is responsible for accepting access requests from the host (processor) bus, and directing all I/O accesses to one of the PCI buses or Legacy I/O locations. If the cycle is directed to one of the PCI Express* segments, the MCH communicates with the PCI Express* devices (add-in card, on board devices) through the PCI Express* interface. If the cycle is directed to the Intel(R) ICH7R, the cycle is output on the MCH's DMI bus. All I/O for the board, including PCI and PC-compatible I/O, is directed through the MCH and then through the Intel(R) ICH7R provided PCI buses. The Intel(R) ICH7R is a multi-function device, housed in a 609-pin mBGA device. It provides the following: A DMI bus A PCI 32-bit/33-MHz interface An IDE interface An integrated Serial ATA Host controller A USB controller A PCI Express* x4 interface A power management controller Each function within the Intel(R) ICH7R has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface. The primary role of the ICH7R controller is providing the gateway to all PC-compatible I/O devices and features. The board uses the following the Intel(R) ICH7R features: PCI 32-bit/33MHz interface for Intel(R) 82541PI Gigabit Ethernet Controller PCI 32-bit/33MHz interface to dedicated ATI* ES1000 video subsystem LPC bus interface x1 PCI Express* interface for Intel(R) 82573E Gigabit Ethernet Controller DMI (Direct Media Interface) Integrated dual-port Serial ATA Host controller Universal Serial Bus (USB) 2.0 interface PC-compatible timer/counter and DMA controllers APIC and 82C59 interrupt controller Power management System RTC
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Supports the SmBUS 2.0 Specification General-purpose I/O (GPIO) The following are the descriptions of how each supported feature is used for the Intel(R) ICH7R on the board. 3.2.2.1.1 SATA Controller
The Intel(R) ICH7R contains four SATA ports. The data transfer rates are up to 150Mbyte/s per port. 3.2.2.2 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The Intel(R) ICH7R provides the functionality of two-cascaded 82C59 with 15 interrupts handling. It supports a processor system bus interrupt. 3.2.2.2.1 Advanced Programmable Interrupt Controller (APIC)
Interrupt generation and notification to the processor is done by the APICs in the Intel(R) ICH7R using messages on the front side bus. 3.2.2.2.2 Universal Serial Bus (USB) Controller
The Intel(R) ICH7R contains one EHCI USB 2.0 controller and four USB ports. The USB controller moves data between main memory and up to four USB connectors. All ports function identically and with the same bandwidth. The Intel(R) Entry Server Board SE7230CA1-E implements four ports on the board. Two external USB ports are provided on the back of the server board. The Universal Serial Bus Specification, Revision 1.1, defines the external connectors. The third/fourth USB port is optional and can be accessed by cabling from an internal 9-pin connector located on the server board to an external USB port located either in front of or the rear of a given chassis. 3.2.2.2.3 Enhanced Power Management
One of the embedded functions of the Intel(R) ICH7R is a power management controller. This is used to implement ACPI-compliant power management features. The server board supports sleep states S0, S1, S4, and S5.
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3.3
Memory Sub-System
The server board supports up to four DIMM sockets for a maximum memory capacity of 8 GB. The DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at 533/667MTs. The memory controller supports the following: Memory scrubbing Single-bit error correction Multiple-bit error detection Intel(R) x4 Single Device Data Correction support with x4 DIMMs Memory can be implemented with either single-sided (one row) or double-sided (two row) DIMMs
3.3.1
Memory Configuration
The memory interface between the MCH and the DIMMs is a 64-bit (non-ECC) or 72-bit (ECC) wide interface. There are two banks of DIMMs, labeled Bank 1 and Bank 2. Bank 1 contains DIMM socket locations DIMM_1A and DIMM_2A. Bank 2 contains DIMM socket locations DIMM_1B and DIMM_2B. The sockets associated with each bank or channel are located next to each other and the DIMM socket identifiers are marked on the server board silkscreen, near the DIMM socket. Bank 1 is associated with Memory Channel A while Bank 2 is associated with Memory Channel B. When only two DIMM modules are being used, the population order must be DIMM_1A, DIMM_1B to ensure dual channel operating mode. In order to operate in dual channel dynamic paging mode, the following conditions must be met: Two identical DIMMs are installed, one each in DIMM_1A and DIMM_1B Four identical DIMMs are installed (one in each socket location) Note: Installing only three DIMMs is not supported. Do not use DIMMs that are not matched (same type and speed). Use of identical memory parts is always the preferred method. DIMM and memory configurations must adhere to the following: DDR2 533/667, un-buffered, DDR2 DIMM modules DIMM organization: x72 ECC or x 64 Non-ECC Pin count: 240 DIMM capacity: 256 MB, 512 MB, 1 GB and 2 GB DIMMs Serial PD: JEDEC Rev 2.0 Voltage options: 1.8 V Interface: SSTL2
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Table 6. Memory Bank Labels and DIMM Population Order
Location J2D1 J1D3 J1D2 J1D1 DIMM Label (DIMM_1A) (DIMM_2A) (DIMM_1B) (DIMM_2B) Channel A A B B 1 3 2 4 Population Order
Figure 3. Memory Bank Label Definition
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Table 7. Characteristics of Dual/Single Channel Configuration with or without Dynamic Mode
Throughput Level Highest Configuration Dual channel with dynamic paging mode Dual channel without dynamic paging mode Single channel with dynamic paging mode Characteristics All DIMMs matched DIMMs matched from Channel A to Channel B DIMMs not matched within channels Single DIMM or DIMMs matched with a channel
Lowest
Single channel without dynamic paging mode
DIMMs not matched
3.3.2
Memory DIMM Support
The board supports un-buffered (not registered) DDR2 533/667 ECC or Non-ECC DIMMs operating at 533/667MT/s. Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on this board. A list of qualified DIMMs is available at http://support.intel.com/support/motherboards/server/. Note all DIMMs are supported by design, but only fully qualified DIMMs will be supported on the board. The minimum supported DIMM size is 256 MB. Therefore, the minimum main memory configuration is 1 x 256 MB or 256 MB. The largest size DIMM supported is 2 GB and as such, the maximum main memory configuration is 8 GB implemented by 4 x 2-GB DIMMs. Only un-buffered DDR2 533/667 compliant, ECC x8 and non-ECC x8 or x16 memory DIMMs are supported. ECC single-bit errors (SBE) will be corrected; multiple-bit error (MBE) will only be detected. Intel(R) Entry Server Board SE7230CA1-E supports Intel(R) x4 Single Device Data Correction with x4 DIMMs. The maximum memory capacity is 8 GB via four 2 GB DIMM modules. The minimum memory capacity is 256 MB via a single 256 MB DIMM module.
3.4
3.4.1
I/O Sub-System
PCI Subsystem
The primary I/O buses for the Intel(R) Entry Server Board SE7230CA1-E are two independent PCI bus segments providing PCI, PCI Express*. The PCI buses comply with the PCI Local Bus Specification, Rev 2.3. PCI Segments A and B are directed through the Intel(R) ICH7R. The following table lists the characteristics of the two PCI bus segments.
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Table 8. PCI Bus Segment Characteristics
PCI Bus Segment A B Voltage 3.3V 3.3V Width 32 bits 1 lane Speed 33MHz 1.5GHz Type PCI 32 x1 PCI Express* NIC 1 NIC 2 PCI I/O Card Slots
3.4.1.1
P32-A: 32-bit, 33-MHz PCI Subsystem
The Intel(R) ICH7R provides a Legacy 32-bit PCI subsystem and acts as the central resource on this PCI interface. P32-A supports the following embedded devices and connectors: One Intel(R) 82541PI Network Controller All 32-bit/33-MHz PCI I/O for the board is directed through the Intel(R) ICH7R. The 32-bit/33-MHz PCI segment created by the Intel(R) ICH7R is known as PCI Segment A. Segment A supports the following embedded device: One 10/100/1000-T Network Interface Controller: Intel(R) 82541PI Gigabit Ethernet Controller. 3.4.1.1.1 Device IDs (IDSEL)
Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD (31:16), which acts as a chip select on the PCI bus segment in configuration cycles. This determines a unique PCI device ID value for use in configuration cycles. The following table shows the bit to which each IDSEL signal is attached for Segment A devices and the corresponding device description.
Table 9. Segment A Configuration IDs
IDSEL Value Device Intel(R) 82541PI LAN (NIC2)
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3.4.1.1.2
Segment A Arbitration
PCI Segment A supports two PCI devices: the Intel(R) ICH7R and one PCI bus masters (NIC). All PCI masters must arbitrate for PCI access, using resources supplied by the Intel(R) ICH7R. The host bridge PCI interface (ICH7R) arbitration lines REQx* and GNTx* are a special case in that they are internal to the host bridge. The following table defines the arbitration connections.
Table 10. Segment A Arbitration Connections
Server Board Signals PCI REQ_N5/GNT_N5 Device Intel(R) 82541PI LAN (NIC2)
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3.4.1.2
PCI Interface for ATI Video subsystem
The graphics subsystem is connected to the Intel(R) ICH7R via a 32/33MHz PCI bus.
3.4.2
Interrupt Routing
The board interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the ICH7R. 3.4.2.1 Legacy Interrupt Routing
For PC-compatible mode, the ICH7R provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is presented to the processors, to which only one processor will respond for servicing. The Intel(R) ICH7R contains configuration registers that define which interrupt source logically maps to I/O APIC INTx pins. The ICH7R handles both PCI and IRQ interrupts. The Intel(R) ICH7R translates these to the APIC bus. The numbers in the following table indicate the Intel(R) ICH7R PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD, INTE, INTF, INTG, INTH for PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is connected. The Intel(R) ICH7R I/O APIC exists on the I/O APIC bus with the processors.
Table 11. PCI Interrupt Routing/Sharing
Interrupt Intel(R) 82541PI ATIES 1000 INT A PIRQB PIRQC INT B INT C INT D
3.4.2.2
APIC Interrupt Routing
For APIC mode, the server board interrupt architecture incorporates three Intel(R) I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel(R) I/O APICs monitor each interrupt on each PCI device; including PCI slots in addition to the ISA compatibility interrupts IRQ (0-15). When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus minimizes interrupt latency time for compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.
3.4.2.3
Legacy Interrupt Sources
The following table recommends the logical interrupt mapping of interrupt sources on the board. The actual interrupt map is defined using configuration registers in the ICH7R.
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Table 12. Interrupt Definitions
ISA Interrupt INTR NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8_L IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 SMI* Floppy disk. Generic Active low RTC interrupt. SCI* Generic Generic Mouse interrupt. Floaty processor. Compatibility IDE interrupt from primary channel IDE devices 0 and 1. Secondary IDE Cable System Management Interrupt. General purpose indicator sourced by the Intel(R) ICH7R to the processors. Description Processor interrupt. NMI to processor. System timer Keyboard interrupt. Slave PIC Serial port 1 interrupt from Super I/O* device, user-configurable. Serial port 1 interrupt from Super I/O* device, user-configurable.
3.4.2.4
Serialized IRQ Support
The Intel(R) Entry Server Board SE7230CA1-E supports a serialized interrupt delivery mechanism. Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame. While in the continuous mode, the start frame is initiated by the host controller.
3.5
PCI Error Handling
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#. All other PCI-related errors are reported by SERR#. SERR# is routed to NMI if enabled by BIOS.
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ICH7R IOAPIC 0 DMI INTERFACE
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23
ICH7R ICH7R 8259PIC
INTR
MCH
CPU
Figure 4. Interrupt Routing Diagram
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Super I/O
Timer Keyboard Cascade Serial Port2/ISA SERIRQ
Serialized IRQ Interface
Serial Port1/ISA ISA Floppy/ISA ISA RTC SCI/ISA ISA ISA Mouse/ISA Coprocessor Error P IDE/ISA Not Used
SERIRQ
ICH7R Interrupt Routing PCI Interface
N/A Intel(R) 82541PI ATI ES1000 N/A N/A N/A N/A N/A
PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH#
Figure 5. Intel(R) ICH7R Interrupt Routing Diagram
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3.5.1
Video Support
The Intel(R) Entry Server Board SE7230CA1-E includes an integrated stand-alone ATI* ES1000 graphics engine that supports standard SVGA drivers with analog display capabilities. The graphics subsystem has 16 MB of dedicated memory to support the onboard video controller. The server board provides a standard 15-pin VGA connector at the rear of the system. 3.5.1.1 Video Modes
Table 13. Video Modes
2D Mode 640x480 800x600 1024x768 1280x1024 1280x1024 1600x1200 1600x1200 3D Mode 640x480 800x600 1024x768 1280x1024 1600x1200 3D Mode 640x480 800x600 1024x768 1280x1024 1600x1200 Refresh Rate (Hz) 60, 72, 75, 90, 100 60, 70, 75, 90, 100 60, 72, 75, 90, 100 43, 60 70, 72 60, 66 76, 85 Refresh Rate (Hz) 60,72,75,90,100 60,70,75,90,100 60,72,75,90,100 43,60,70,72 60,66,76,85 Refresh Rate (Hz) 60,72,75,90,100 60,70,75,90,100 60,72,75,90,100 43,60,70,72 60,66,76,85 8 bpp Supported Supported Supported Supported Supported 8 bpp Supported Supported Supported Supported Supported 8 bpp Supported Supported Supported Supported Supported Supported Supported 2D Video Mode Support 16 bpp 24 bpp Supported Supported Supported Supported Supported - Supported Supported Supported Supported Supported Supported Supported Supported
32 bpp Supported Supported Supported Supported Supported Supported -
3D Video Mode Support with Z Buffer Enabled 16 bpp 24 bpp 32 bpp Supported Supported Supported Supported Supported Supported - Supported Supported - - Supported Supported - -
3D Video Mode Support with Z Buffer Disabled 16 bpp 24 bpp 32 bpp Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported - Supported Supported - -
3.5.2
Network Interface Controller (NIC)
The Intel(R) Entry Server Board SE7230CA1-E supports two 10/100/1000 Base-T network interfaces. NIC1 is an Intel(R) 82573E Gigabit Ethernet Controller resourced with a x1 PCI Express* interface from the Intel(R) ICH7R (PCI Segment B). NIC2 is an Intel(R) 82541PI Gigabit Ethernet Controller resourced with a 32bit/33MHz PCI Segment from the Intel(R) ICH7R (PCI Segment A).
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Both the Intel(R) 82573E and Intel(R) 82541PI Gigabit Ethernet Controllers are single, compact components with an integrated gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) function. The Intel(R) 82573E and Intel(R) 82541PI Gigabit Ethernet Controller allow for a gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel(R) 82541PI Gigabit Ethernet Controller and Intel(R) 82573E integrate fourth and fifth generation (respectively) gigabit MAC design with fully integrated physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz. 3.5.2.1 NIC Connector and Status LEDs
The NICs drive two LEDs located on each network interface connector.
Table 14. Intel(R) 82573E (NIC 1 and NIC 2)
LED Left Color Off Green N/A Right Green Yellow On Blinking Off On On LED State Condition LAN link is not established. LAN link is established. LAN activity is occurring. 10 Mbit/sec data rate is selected. 100 Mbit/sec data rate is selected. 1000 Mbit/sec data rate is selected.
3.5.3
Super I/O Chip
The SMsC* LP47M182NR SIO devices contain all of the necessary circuitry to control the serial/parallel ports, floppy disk, PS/2-compatible keyboard, mouse and hardware monitor controller. The server board implements the following features: GPIOs Two serial port Local hardware monitoring Wake up control System health support 3.5.3.1 Serial Ports
The board provides a serial port implemented as an external 9-pin serial port; an internal 9-pin serial port is also provided. The following sections provide details on the use of the serial port.
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3.5.3.1.1
Serial Port A
Serial A is a standard DB9 interface located at the rear I/O panel of the server board, above the video connector. Serial A is designated by a Serial_A on the silkscreen. The reference designator is J3A1. Serial B is a 9-pin header interface located near the DIMMs. Serial B is designated by a Serial_B on the silkscreen. The reference designator is J1C2.
Table 15. Serial A Header Pin-out
Pin 1 2 3 4 5 6 7 8 9 DCD RX TX DTR GND DSR RTS CTS RI Signal Name Serial Port A Header Pin-out
Table 16. Serial B Header Pin-out
Pin 1 2 3 4 5 6 7 8 9 DCD DSR RX RTS TX CTS DTR RI GND Signal Name Serial Port B Header Pin-out
3.5.3.2
Keyboard and Mouse Support
USB ports can be used to support keyboard and mouse. 3.5.3.3 Wake-up Control
The Super I/O contains functionality that allows various events to control the power-on and power-off the system.
3.5.4
BIOS Flash
The board incorporates an 8-MB firmware Hub flash memory component. This flash device is connected through the LPC bus from the ICH7R controller.
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3.5.5
2
System Health Support
The I C interface to the Heceta* sensors (fan monitor and control [FMC]) support: One PWM-based fan control Software or local temperature feedback control Chassis intrusion detection
3.6
Replacing the Back-Up Battery
The lithium battery on the server board powers the RTC for up to ten years in the absence of power. When the battery starts to weaken, it loses voltage, and the server settings stored in CMOS RAM in the RTC (for example, the date and time) may be wrong. Contact your customer service representative or dealer for a list of approved devices. WARNING Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the equipment manufacturer. Discard used batteries according to manufacturer's instructions. ADVARSEL! Lithiumbatteri - Eksplosionsfare ved fejlagtig handtering. Udskiftning ma kun ske med batteri af samme fabrikat og type. Lever det brugte batteri tilbage til leverandoren. ADVARSEL Lithiumbatteri - Eksplosjonsfare. Ved utskifting benyttes kun batteri som anbefalt av apparatfabrikanten. Brukt batteri returneres apparatleverandoren. VARNING Explosionsfara vid felaktigt batteribyte. Anvand samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren. Kassera anvant batteri enligt fabrikantens instruktion. VAROITUS Paristo voi rajahtaa, jos se on virheellisesti asennettu. Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin. Havita kaytetty paristo valmistajan ohjeiden mukaisesti.
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4.1
System BIOS
BIOS Setup Utility
The BIOS Setup Utility is provided to perform system configuration changes and to display current settings and environment information. The BIOS Setup Utility stores configuration settings in system non-volatile storage. Changes affected by BIOS Setup will not take effect until the system is rebooted. The BIOS Setup Utility can be accessed when prompted during POST by using the F2 key.
4.1.1
Localization
The BIOS Setup program and help messages currently support up to six languages. However, depending upon space requirements, the following applies with regard to language support. Flex BIOS handles languages based upon OEM requirements. This is a stretch goal. The default language is US English. This is the only language that is guaranteed to be properly translated and functional.
4.1.2
Configuration Reset
There are different mechanisms for resetting the system configuration to default values. When a reset system configuration request is detected, the BIOS will load the default system configuration values during the next POST. A reset system configuration request can be generated by moving the Clear CMOS jumper.
4.1.3
Keyboard Commands
The bottom right portion of the Setup screen provides a list of commands that are used to navigate through the Setup utility. These commands are displayed at all times. Each Setup menu page contains a number of features. Except those used for informative purposes, each feature is associated with a value field. This field contains user-selectable parameters. Depending on the security option chosen and in effect by the password, a menu feature's value may or may not be changeable. If a value is non-changeable, the feature's value field is inaccessible. It displays as "grayed out." The Keyboard Command Bar supports the following keys.
Table 17. BIOS Setup Keyboard Command Bar Options
Key Enter Option Execute Command Description The Enter key is used to activate sub-menus when the selected feature is a sub-menu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date. If a pick list is displayed, the Enter key will undo the pick list, and allow another selection in the parent menu.
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Key ESC
Option Exit
Description The ESC key provides a mechanism for backing out of any field. This key will undo the pressing of the Enter key. When the ESC key is pressed while editing any field or selecting features of a menu, the parent menu is re-entered. When the ESC key is pressed, any sub-menu, the parent menu is re-entered. When the ESC key is pressed, any major menu, the exit confirmation window is displayed and the user is asked whether changes can be discarded. If No is selected and the Enter key is pressed, or if the ESC key is pressed, the user is returned to where they were before ESC was pressed without affecting any existing any settings. If Yes is selected and the Enter key is pressed, setup is exited and the BIOS continues with POST. The up arrow is used to select the previous value in a pick list, or the previous options in a menu item's option list. The selected item must then be activated by pressing the Enter key. The down arrow is used to select the next value in a menu item's option list, or a value field's pick list. The selected item must then be activated by pressing the Enter key. The left and right arrow keys are used to move between the major menu pages. The keys have no affect if a sub-menu or pick list is displayed. The Tab key is used to move between fields. For example, Tab can be used to move from hours to minutes in the time item in the main menu. The minus key on the keypad is used to change the value of the current item to the previous value. This key scrolls through the values in the associated pick list without displaying the full list. The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboard, but will have the same effect. Pressing F9 causes the following to appear: Load Setup Defaults? [OK] [Cancel] If OK is selected and the Enter key is pressed, all setup fields are set to their default values. If Cancel is selected and the Enter key is pressed, or if the ESC key is pressed, the user is returned to where they were before F9 was pressed without affecting any existing field values.
Select Item
Tab -
Select Item Select Menu Select Field Change Value
+
Change Value
F9
Setup Defaults
F10
Save Changes and Exit
Pressing F10 causes the following message to appear: Save configuration changes and exit setup? [OK] [Cancel] If OK is selected and the Enter key is pressed, all changes are saved and setup is exited. If Cancel is selected and the Enter key is pressed, or the ESC key is pressed, the user is returned to where they were before F10 was pressed without affecting any existing values.
4.1.4
Entering BIOS Setup
The BIOS Setup Utility can be accessed by pressing the [F2] hotkey during POST.
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4.1.4.1
Main Menu
The first screen displayed when entering the BIOS Setup Utility is the Main Menu selection. This screen displays the major menu selections available. The following tables describe the available options on the top-level and lower-level menus. Default values are in bold text.
Table 18. BIOS Setup, Main Menu Options
Feature BIOS Version Processor Type Hyper Threading Technology Processor speed System Bus speed System Memory speed L2 Cache RAM Total Memory Memory Mode Memory Channel 1A Memory Channel 2A Memory Channel 1B Memory Channel 2B Additional System Information System Date Options N/A N/A Enable Disable N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAY MM/DD/YYYY N/A N/A N/A Select disable if your operating system does not support Hyper Threading Calculates processor speed Displays the system bus speed Displays the system memory speed Help Text Description BIOS ID string (excluding the build time and date)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Use [TAB] or [SHIFT-TAB] to select a field. Use [+] or [-] to configure system date. Use [TAB] or [SHIFT-TAB] to select a field. Use [+] or [-] to configure system time.
Detects amount of physical memory Displays the memory mode Displays the memory detected
Selects submenu with additional system information details Configures the system date. Default is [Tue 01/01/2002]. Day of the week is automatically calculated Configures the system time on a 24-hour clock. Default is 00:00:00
System Time
HH:MM:SS
4.1.4.1.1
Additional System Information Sub-menu
Table 19. BIOS Setup, Additional System Information Sub-menu Selections
Feature System Information Manufacturer N/A
Options
Help Text
Description Informational display.
N/A
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Feature Product Name Version Serial Number Server Board Information Manufacturer Product Name Version Serial Number Chassis Information Manufacturer Version Serial Number Asset Tag
Options N/A N/A N/A N/A N/A N/A
Help Text
Description
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
4.1.4.2
Advanced Menu
Table 20. BIOS Setup, Advanced Menu Options
Feature Boot configuration Peripheral configuration Drive configuration Event log configuration Video configuration Hardware monitoring Chipset configuration Management configuration USB configuration
Options N/A N/A N/A N/A N/A N/A N/A N/A N/A
Help Text Configure boot devices Configure peripheral devices Configure primary master slave and secondary master and slave View the events in the event log or clear current events Configure video Configure hardware monitoring Configure chipset Configure management Configure USB support.
Description Selects submenu Selects submenu Selects submenu Selects submenu Selects submenu Selects submenu Selects submenu Selects submenu Selects submenu
4.1.4.2.1
Boot Configuration Sub-menu
Table 21. BIOS Setup, Advanced Menu, Boot Configuration Sub-menu Selections
Feature CPU Fan Control System Fan Control Options Disable Enable Disable Enable Help Text Enable or Disable CPU fan control N/A Description
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Feature Lowest Fan speed
Options Slow Off
Help Text These options define the lower limit of chassis fan speed operation. Slow: At low system temperatures, the fans will continue to run at a slow speed. Off: At low system temperatures, the fans will turn off. This should be enabled in order to boot legacy operating systems that cannot support CPUs with extended CPUID functions Displays "Press F2 to Enter Setup" message during POST
Description
Max CPUID Value Limit
Disable Enable Off On
Display Setup Prompt
4.1.4.2.2
Peripheral Configuration Sub-menu
Table 22. BIOS Setup, Advanced Menu, Peripheral Configuration Sub-menu
Feature Serial Port A Serial Port B PCI Express* Onboard LAN PCI On-board LAN
Options Disable Enable Disable Enable Disable Enable Disable Enable
Help Text Enable or Disable the On board Serial port Enable or Disable the On board Serial port Enable or Disable the PCI Express* On-board LAN Device (NIC1 Intel 82573E) Enable or Disable the PCI On-board LAN Device (NIC2 Intel 82541PI)
Description
4.1.4.2.3
Drive Configuration Sub-menu
Table 23. BIOS Setup, Advanced Menu, Drive Configuration Menu Options
Feature Use Automatic Mode Use Serial ATA as ATA/IDE Mode
Options Disable Enable Enable Disable Legacy Enhanced
Help Text
Description
Enable or Disable the onboard Serial ATA ports Configure SATA for either Enhanced (native) or Legacy mode Configure SATA into the appropriate type S.M.A.R.T. stands for SelfMonitoring, Analysis, and Reporting Technology N/A Controls state of integrated S-ATA and P-ATA controller. In Enhance mode this item will display. The Auto setting should work in most cases. Displays the SATA HDD detected
Configure SATA as
IDE RAID AHCI Enable Disable N/A
S.M.A.R.T.
SATA Port 0
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Feature SATA Port 1 Hard Disk Pre-Delay (Sec)
Options N/A 0 5 10 15 20 25 30 35 N/A
Help Text Indicates the amount of time in seconds that the firmware will wait to detect hard disk drives
Description Displays the SATA HDD detected
4.1.4.2.4
Event Log Configuration Sub-menu
Table 24. BIOS Setup, Advanced Menu, Event Log Configuration Sub-menu Selections
Feature View Event Log Clear Event Log Options Disable Enable Disable Enable Disable Enable Help Text Views the events Clears the events Description When Disable is selected, the event log will be cleared during the next system reset Enables/Disables the event log Enables/Disables ECC Events recorded in the event log
Event Logging ECC Event Logging
4.1.4.2.5
Video Configuration Sub-menu
Table 25. BIOS Setup, Advanced Menu, Video Configuration Sub-menu Selections
Feature Console Redirection Serial Port Options Disable Enable Help Text Enable/Disable Console Redirection via Serial Port (COM1). Video resolution set to 640x480. Serial Port baud rate set to 57600 Description
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Hardware Monitoring
Table 26. BIOS Setup, Advanced Menu, Hardware Monitoring Sub-menu Selections
Feature Hardware Monitoring Display H/W Settings Processor Fan Speed System Fan1 Speed System Fan2 Speed Processor Temp Internal Temp V12.0 V5.0 V3.3 V1.5 Vccp Options N/A N/A Help Text Description
N/A 2280 0000 0000 64 C 34 C 12.000 V 5.084 V 3.250 V 1.516 V 1.324 V
N/A
Selects submenu, determined by the real system.
4.1.4.2.7
Chipset Configuration Sub-menu Selections
Table 27. BIOS Setup, Advanced Menu, Chipset Configuration Sub-menu Selections
Feature Memory Configuration PCI Express* Configuration PCI Latency timer Options N/A N/A 32 64 96 128 160 192 224 248 N/A N/A Help Text Description Selects submenu with memory configuration details Selects submenu with PCI Express* configuration details
4.1.4.2.7.1 Memory Configuration Sub-menu This sub-menu provides information about the DIMMs detected by the BIOS. The DIMM number is printed on the server board next to each device.
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Table 28. BIOS Setup, Advanced Menu, Chipset Configuration, Memory Configuration Sub-menu Selections
Feature Memory correction Options Non-ECC ECC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Help Text Allow the user to turn error reporting on or off if the system and all the memory installed supports ECC (Error Correction Code) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Informational display Description
Memory frequency SDRAM tCL SDRAM tRCD SDRAM tRP SDRAM tRASmin DDR2 voltage Total memory Memory mode DIMM 1A DIMM 2A DIMM 1B DIMM 2B
4.1.4.2.7.2 PCI Configuration Sub-menu This sub-menu provides control over PCI devices and their option ROMs. If the BIOS is reporting POST error 146, use this menu to disable option ROMs that are not required to boot the system.
Table 29. BIOS Setup, Advanced Menu, Chipset Configuration, PCI Express* Configuration Submenu Selections
Feature PEG Negotiated Width Compliance Test Pattern Options N/A Disable Enable Help Text N/A N/A Description
4.1.4.2.8
Management Configuration Sub-menu
Table 30. BIOS Setup, Advanced Menu, Management Configuration Sub-menu Selections
Feature Enter Intel@ AMT BX Setup Options Disable Enable Help Text Allows Intel(R) AMT to be force enabled or disabled. Also controls ability to individually set AMTBX, SOL, IDER capabilities. Description
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4.1.4.2.9
USB Mass Storage Device Configuration Sub-menu
Table 31. BIOS Setup, Advanced Menu, USB Mass Storage Device Configuration Sub-menu Selections
Feature USB 2.0 Options Enable Disable N/A Help Text Description Enable/Disable all USB ports
4.1.4.3
Security Menu
Table 32. BIOS Setup, Security Menu Options
Feature Supervisor password User password Set supervisor password Set user password
Options N/A N/A N/A N/A
Help Text Install / Not install Install / Not install Set supervisor password Set user password
Description Informational display Informational display Set password to null to clear This node is grayed out until Admin password is installed. Set password to null to clear. Chassis intrusion enable will log chassis intrusion to the event log Enables/Disables the CPU execute disable bit.
Chassis intrusion XD technology
Disable Enable Disable Enable
N/A N/A
4.1.4.4
Power Menu
Table 33. BIOS Setup, Power Menu Selections
Feature After Power Failure
Options Stay off Last State Power On
Help Text Determines the mode of operation if a power loss occurs. Stays Off: System will remain off once power is restored. Last State: Restores system to the same state it was before power failed. Power On: System will power on once power is restored. Determines the action taken when the system power is off and a PCI Power management wake-up event occurs.
Description
Wake on LAN from S5
Stay Off Power On
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4.1.4.5
Boot Menu
Table 34. BIOS Setup, Boot Menu Selections
Feature Boot menu type Boot device priority Hard drive order
Options Normal Advance Varies Varies
Help Text N/A N/A N/A
Description
Select the boot drive order Select the boot order of available hard drive devices Select the boot order of available CD/DVD devices Select the boot order of removable devices
CD/DVD-ROM drive order
Varies
N/A
Removable drive order
Varies
N/A
Boot to optical devices Boot to removable devices Boot to network USB boot Zip emulation type
Disable Enable Disable Enable Disable Enable Disable Enable
Enables or disables boot to optical devices Enables or disables boot to removable devices Enables or disables boot to network Enables or disables USB boot
Sets the emulation type for zip drives Floppy Hard Disk
4.1.4.6
Exit menu
Table 35. BIOS Setup, Exit Menu Selections
Feature Exit saving changes Exit discarding changes Load optimal defaults Load custom defaults Save custom defaults Discard changes
Options N/A N/A N/A N/A N/A N/A
Help Text Exit system setup after saving the changes. F10 key can be used for this operation. Exit system setup without saving any changes. ESC key can be used for this operation. Load Setup default values for all the setup questions. F9 key can be used for this operation. Load custom defaults. Save custom defaults. Discard changes done so far to any of the setup questions.
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The BIOS Setup Utility is a text-based utility that allows the user to configure the system and view current settings and environment information for the platform devices. The Setup Utility controls the platform's built-in devices. The BIOS Setup interface consists of a number of pages or screens. Each page contains information or links to other pages. The first page in Setup displays a list of general categories as links. These links lead to pages containing a specific category's configuration. The following sections describe the look and behavior for platform Setup.
4.1.5
Operation
BIOS Setup has the following features: Localization: BIOS Setup uses the Unicode standard and is capable of displaying Setup forms in all languages currently included in the Unicode standard. The Intel(R) Server Board BIOS will only be available in English. BIOS Setup is functional via console redirection over various terminal emulation standards. This may limit some functionality for compatibility, e.g., usage of colors or some keys or key sequences or support of pointing devices. 4.1.5.1 Setup Page Layout
The setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area.
Table 36. BIOS Setup Page Layout
Functional Area Title Bar Setup Item List Description The title bar is located at the top of the screen and displays the title of the form (page) the user is currently viewing. It may also display navigational information. The Setup Item List is a set of controllable and informational items. Each item in the list occupies the left and center columns in the middle of the screen. The left column, the "Setup Item", is the subject of the item. The middle column, the "Option", contains an informational value or choices of the subject. A Setup Item may also be a hyperlink that is used to navigate formsets (pages). When it is a hyperlink, a Setup Item only occupies the "Setup Item" column. The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item. Help information includes the meaning and usage of the item, allowable values, effects of the options, etc. The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys. The keyboard command bar is context-sensitive--it displays keys relevant to current page and mode. The Status Bar occupies the bottom line of the screen. This line would display the BIOS ID.
Item Specific Help Area
Keyboard Command Bar
Status Bar
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4.1.5.2
Entering BIOS Setup
BIOS Setup is started by pressing during boot time when the OEM or Intel logo is displayed. When Quiet Boot is disabled, there will be a message "press to enter setup" displayed on the diagnostics screen. 4.1.5.3 Menu Selection Bar
The Menu Selection Bar is located at the top of the screen. It displays the major menu selections available to the user.
4.2
4.2.1
4.2.1.1
Flash Memory Update Utility
BIOS Update
DOS Flash Utility
The BIOS can be upgraded from a HDD, diskette or CD-ROM using the Intel(R) iFlash Utility. This utility supports the following functions: * Updates the BIOS from a file or file set * Verifies that the upgrade BIOS matches the target system to prevent accidentally installing an incompatible BIOS * RPM support (this includes VBIOS update, etc.). RPM support is a stretch goal. 4.2.1.2 iFlash Update Version Checking
When Flash BIOS Updates and Flash Language Updates are performed, a certain amount of identification information will be checked before allowing the process to proceed. This checking prevents a BIOS from being flashed into the wrong system, possibly causing boot failure. This checking also prevents an incoherent language file from being flashed into a functional machine. 4.2.1.3 Standard Flash BIOS Updates Whenever a Flash BIOS Update is performed, the Board Identifier, the Board Revision and the OEM Identifier must match. 4.2.1.4 Flash Language Updates Whenever Flash Language Updates are performed, the Board Identifier, Board Revision, OEM Identifier and Build Identifier must match. 4.2.1.5 RPM (Replaceable Program Modules) Updates
Whenever RPM operations are performed, the Board Identifier and Board Revision must match. This currently only applies to video OPROM code. RPM support is a stretch goal.
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4.2.2
O/S Present Flash Utility
The BIOS can be upgraded from a HDD, diskette or CD-ROM using the Intel(R) Express BIOS Update utility. This utility supports the following functions: Updates the BIOS from a file or file set Verifies that the upgrade BIOS matches the target system to prevent accidentally installing an incompatible BIOS Works under Microsoft Windows 2000* and Microsoft Windows XP*
4.3 DMI/SMBIOS Support
4.3.1 DMI/SMBIOS Write Tool
A DMI/SMBIOS write utility allows OEMs to write their specific data into SMBIOS structures type 1 and 3 (chassis info - asset tag field only).
4.4
4.4.1
Operating System Boot, Sleep, and Wake
Boot Device Selection
The Boot Device Selection phase is responsible for controlling the boot of the system. The boot option variables are set by an operating system during operating system installation or manually added by the user through the Boot Maintenance Manager of Setup. The Boot Maintenance Manager provides the capability to make permanent changes to the boot order. It is also possible to change the first boot option for a single boot. 4.4.1.1 Server Management Boot Device Control
The IPMI 2.0 specification includes provisions for server management devices to set certain boot parameters by setting boot flags. Among the boot flags (parameter #5 in the IPMI specification) the BIOS will check data 1-3 for forced boot options. The BIOS supports forced booting from the following: PXE HDD (USB, SATA and PATA) USB FDD USB key CD-ROM drive On each boot, the BIOS invokes the Get System Boot Options command to determine what changes to boot options have been set. The BIOS takes the appropriate action and clears these settings.
4.4.2
4.4.2.1
Operating System Support
Microsoft Windows* Compatibility
Intel Corporation and Microsoft Corporation co-author design guides for system designers who will use Intel(R) processors and Microsoft* operating systems. The Hardware Design Guide for Microsoft Windows 2000 Server, Version 3.0 is intended for systems that are designed to work
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with Windows Server* class operating systems. The specification further classifies the systems and includes sets of requirements based on the intended usage for that system. For example, a server system that is used in small home / office environments has different requirements than one used for enterprise applications. This product supports the Hardware Design Guide for Microsoft Windows 2000 Server, Version 3.0 enterprise requirements. 4.4.2.2 Advanced Configuration and Power Interface (ACPI)
The primary role of the ACPI BIOS is to supply the ACPI tables. POST creates the ACPI tables and locates them in extended memory (above 1 MB). The location of these tables is conveyed to the ACPI-aware operating system through a series of tables located throughout memory. The format and location of these tables is documented in the publicly available ACPI specifications (Advanced Configuration and Power Interface Specification, Revision 1.0b and Advanced Configuration and Power Interface Specification, Revision 2.0). The BIOS supports both ACPI 2.0 and 1.0b tables. To prevent conflicts with a non-ACPI-aware operating system, the memory used for the ACPI tables is marked as "reserved" in INT 15h, function E820h. As described in the ACPI specifications, an ACPI-aware operating system generates an SMI to request that the system be switched into ACPI mode. The BIOS responds by setting up all system (chipset) specific configurations required to support ACPI, issues the appropriate command to enable ACPI mode, and sets the SCI_EN bit as defined by the ACPI specification. The system automatically returns to legacy mode on hard reset or power-on reset. There are three runtime components to ACPI: ACPI Tables: These tables describe the interfaces to the hardware. ACPI tables can make use of ACPI Machine Language (AML), the interpretation of which is performed by the operating system. The operating system contains and uses an AML interpreter that executes procedures encoded in AML and is stored in the ACPI tables. AML is a compact, tokenized, abstract machine language. The tables contain information about power management capabilities of the system, APICs, and bus structure. The tables also describe control methods that the operating system uses to change PCI interrupt routing, control legacy devices in the Super I/O, find out the cause of a wake event, and handle PCI hot plug, if applicable. ACPI Registers: This is the constrained part of the hardware interface, described (at least in location) by the ACPI tables. ACPI BIOS: This is the code that boots the machine and implements interfaces for sleep, wake, and some restart operations. The ACPI Description Tables are also provided by the ACPI BIOS. The ACPI specification requires the system to support at least one sleep state. The BIOS supports S0, S1, S4, and S5 states. S1 is considered a sleep state.
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This platform can wake up from S1 state using USB devices in addition to the sources described below. The wake-up sources are enabled by the ACPI operating systems with cooperation from the drivers; the BIOS has no direct control over the wakeup sources when an ACPI operating system is loaded. The role of the BIOS is limited to describing the wakeup sources to the operating system and controlling secondary control / status bits via the Differentiated System Description Table (DSDT). The S5 state is equivalent to operating system shutdown. No system context is saved when going into S5. The OEM Table ID field of ACPI Tables are initialized with the Platform Identification string.
4.4.3
Front Control Panel Support
The platform supports a power button and a reset button on the control panel. 4.4.3.1 Power Button
The BIOS supports a front control panel power button. Pressing the power button initiates a request, which is forwarded to the ACPI power state machines in the chipset. 4.4.3.2 Reset Button
The platform supports a front control panel reset button. Pressing the reset button initiates a request to the chipset.
4.4.4
4.4.4.1
Sleep and Wake Support
System Sleep States
The platform supports the following ACPI system sleep states: ACPI S0 (working) state ACPI S1 (sleep) state ACPI S4 (hibernate) state ACPI S5 (soft-off) state 4.4.4.2 Wake Events / SCI Sources
The server board supports the following wake-up sources in the ACPI environment. The operating system controls enabling and disabling these wake sources: Devices that are connected to all USB ports, such as USB mice and keyboards can wake the system up from S1 sleep state. PCI devices, such as onboard NIC devices, can wake the system from the S4/S5 state. As required by ACPI specification, the power button can wake the system from S1 state
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5.
Server Management
The BIOS supports many standards-based server management features and several proprietary features.
5.1
Console Redirection
The BIOS supports redirection of both video and keyboard via a serial link (COM port). When console redirection is enabled, the local (host server) keyboard input and POST video output are passed both to the local keyboard and video connections, and to the remote console through the serial link. Keyboard inputs from both sources are considered valid and video is displayed to both outputs. As an option, the system can be operated without a host keyboard or monitor attached to the system and run entirely via the remote console, including BIOS Setup.
5.1.1
Serial Configuration Settings
Both EMP and console redirection require N, 8, 1 mode (no parity, 8-bit data, 1 stop bit). The BIOS does not require that the splash logo be turned off for console redirection to function. The BIOS supports multiple consoles, some of which are in graphics mode and some in text mode. The graphics consoles can display the logo and the text consoles can receive the redirected text. Console redirection ends at the beginning of the legacy operating system boot (INT 19h). The operating system is responsible for continuing the redirection from that point.
5.1.2
Keystroke Mappings
During console redirection, the remote terminal sends keystrokes to the local server. The remote terminal may be a dumb terminal with a direct connection running a communication program. The keystroke mappings follow VT-UTF8 format with the following extensions. 5.1.2.1 Setup Alias Keys
The and -function key combinations are synonyms for the or "Setup" key. They are implemented and documented, but are not to be prompted for in screen messages. These hot keys are defined for console redirection support, and are not to be implemented for locally attached keyboards. 5.1.2.2 Standalone Key for Headless Operation
The Microsoft Headless Design Guidelines describes a specific implementation for the key as a single standalone keystroke: followed by a two-second pause must be interpreted as a single escape. followed within two seconds by one or more characters that do not form a sequence described in this specification must be interpreted as plus the character or characters, not as an escape sequence.
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The escape sequence in the following table is an input sequence. This means it is sent to the BIOS from the remote terminal.
Table 37. Console Redirection Escape Sequences for Headless Operation
Escape Sequence RrR This will implement but will default to "disabled". Description Remote Console Reset
5.1.3
Limitations
BIOS Console redirection terminates after an EFI-aware operating system calls EFI Exit Boot Services. The operating system is responsible for continuing console redirection after that. BIOS console redirection is a text console. Graphical data, such as a logo, are not redirected.
5.2
Intel(R) Active Management Technology (AMT)
Intel Active Management Technology architecture is based on market demand for a platform management solution that provides remote management capabilities independent of system power states. The Intel(R) AMT architecture is centered around the Intel(R) ICH7R IO controller and Intel(R) 82573E Gigabit LAN components. The ICH7R provides an interface to a new SPI flash device for potential cost savings. Because Intel(R) AMT depends on the availability of the Intel(R) 82573E PCI manageability functions, the Intel(R) AMT does not operate with third-party LANs. The main objectives of Intel AMT are: Deployable - Intel(R) AMT uses existing protocols and services available in today's IT networks to minimize cost. Intel(R) AMT is constrained to the use of DHCP, DNS, SOAP/XML/HTTP, and TLS; which are available on most IT networks today. Highly Available - The ability to provide remote management in the event of operating system or hardware failure. Intel(R) AMT provides baseline services whenever there is (at the minimum) auxiliary power available to the platform. Currently, system auxiliary power is maintained by the main power supply when the system is plugged into the wall. This will significantly reduce IT expenses for system repair. OS-Independent Agent - Baseline platform management capabilities that simplify system management running different operating system types and versions. Intel(R) AMT provides common remote management and persistent storage features that run independently of the operating system. Secure and Tamper Resistant - Intel(R) AMT provides access control, data security, and protection against attacks by using standard security protocols (e.g., TLS) and application-level security mechanisms. Intel(R) AMT also provides tamper resistance to prevent the end-user from removing or disabling remote management service.
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Intel(R) 82573E is a multi-functional device with an embedded microcontroller for manageability purposes. Manageability functions of the Intel(R) 82573E PCI are as follows: IDE-R - for remote boot and SW installation Serial Port - for Keyboard and text redirection KCS - for configuration of the manageability content
The Intel(R) 82573E controller is a PCI Express* GBit Ethernet endpoint device, the first GbE controller to support Intel(R) AMT as the next-generation client manageability architecture. Intel(R) 82573E provides three PCI functions for management purposes: serial port, IDE, and KCS. When the Intel(R) AMT is disabled, the Intel(R) 82573E controller disables these three PCI functions. When these management functions are disabled, the functions do not response to PCI configuration cycles (effectively becoming invisible to software). When Intel(R) AMT is enabled, the Intel(R) 82573E controller enables the PCI functions, which appear to software as standard PCI devices. Serial Port Function: The Serial Port function supports redirection of keyboard and POST messages to a terminal window on a remote console. The keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. Text and keyboard redirection allows the remote machine to monitor POST progress of the client machine and allows the remote machine to control and configure the client by entering BIOS Setup. The Intel(R) 82573E controller redirects data from the serial port to the management console via the LAN; hence, providing Serial Over LAN (SOL) capability. IDE Function: The IDE function provides IDE-R, an IDE redirection interface that provides client connection to management console ATA/ATAPI devices. When booting from IDE-R, the IDE-R interface will send the client's ATA/ATAPI command to the management console. The management console responds back to the client. A remote machine can setup diagnostic software or an operating system installation image and direct the client to boot from IDE-R. The IDE-R interface is the same as the IDE interface and is compliant with ATA/ATAPI-6 specifications. IDE-R does not conflict with the usage of PXE boot. The system can support both interfaces and can continue to boot from PXE as with any other boot devices. However, during a management boot session, the Intel(R) AMT solution will use IDE-R when remote boot is required. The devices attached to the IDE-R channel are only visible to software during a management boot session. During a normal boot session, the IDE-R channel appears as no device present. KCS Function: The KCS (Keyboard Controller Style) function provides a physical interface used to convey messages between the host software and the AMT device. The KCS function defines a set of memory-mapped IO (MMIO) registers. These MMIO registers follow the usage model used in the Intel(R) 8742 Universal Peripheral Interface microcontroller. The term `Keyboard Controller Style' reflects the fact that the Intel(R) 8742 interface is used as the system keyboard controller interface in PC architecture computer systems. The AMT BIOS Extension (AMTx) is provided by Intel and is included in the system BIOS at build time. The AMTx Module communicates with the Intel(R) 82573E firmware via the KCS interface. The AMTx Module collects system hardware configuration via ACPI and the SMBIOS tables, and sends hardware information to the remote management system via the KCS interface.
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Table 38. Function List
Function Intel(R) 82573E Lan IDE Serial Port KCS Vendor ID 0x8086 0x8086 0x8086 0x8086 Device ID 0x108B/0x108C (V/E) 0x108D 0x108F 0x108E
5.3
Wired For Management (WFM)
Wired for Management is an industry-wide initiative to increase overall manageability and reduce total cost of ownership. WFM allows a server to be managed over a network. The system BIOS supports the System Management BIOS Reference Specification, Version 2.4 to help higher-level instrumentation software meet the Wired For Management Baseline Specification, Revision 2.0 requirements.
5.3.1
PXE BIOS Support
The BIOS supports the EFI PXE implementation as specified in Chapter 15 of the Extensible Firmware Interface Reference Specification, Version 1.1. To utilize this, the user must load the EFI Simple Network Protocol driver. The UNDI driver is specific to the network controller and must be included with the network card. The Simple Network Protocol driver can be obtained from http://developer.intel.com/technology/framework. The BIOS supports legacy PXE option ROMs in legacy mode and includes the necessary PXE ROMs in the BIOS image for the onboard controllers. The legacy PXE ROM is required to boot a non-EFI operating system over the network.
5.4
System Management BIOS (SMBIOS)
The BIOS provides support for the System Management BIOS Reference Specification, Version 2.4 to create a standardized interface for manageable attributes that are expected to be supported by DMI-enabled computer systems. The BIOS provides this interface via data structures through which the system attributes are reported. Using SMBIOS, a system administrator can obtain the types, capabilities, operational status, installation date and other information about the server components.
5.5
Security
The BIOS provides several security features. This section describes the security features and operating model.
5.5.1
Operating Model
The following table summarizes the operation of security features supported by the BIOS.
Table 39. Security Features Operating Model
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Mode Password on boot
Entry Method / Event Power On / Reset
Entry Criteria User password set and password on boot enabled in BIOS Setup. Secure boot disabled in BIOS Setup.
Behavior System halts for user password before scanning option ROMs. The system is not in secure mode. No mouse or keyboard input is accepted except the password.
Exit Criteria User password. Administrator password.
After Exit Front control panel buttons are reenabled. The server boots normally. Boot sequence is determined by setup options.
5.5.2
Password Protection
The BIOS uses passwords to prevent unauthorized tampering with the server setup. Both user and administrator passwords are supported by the BIOS. An Administrator password must be entered in order to set the user password. The maximum length of a password can be seven characters. The password cannot have characters other than alphanumeric (a-z, A-Z, 0-9). It is not case sensitive. Once set, a password can be cleared by changing it to a null string. Entering the user password will allow the user to modify the time, date, and user password. Other setup fields can be modified only if the administrator password is entered. If only one password is set, this password is required to enter BIOS Setup. The administrator has control over all fields in BIOS Setup, including the ability to clear the user password. If the user or administrator enters an incorrect password three times in a row during the boot sequence, the system is placed into a halt state. A system reset is required to exit out of the halt state. This feature makes it difficult to break the password by guessing at it.
5.5.3
Password Clear Jumper
If the user and/or administrator password is lost or forgotten, both passwords may be cleared by moving the password clear jumper into the clear position. The BIOS determines if the password clear jumper is in the clear position during BIOS POST and clears any passwords if required. The password clear jumper must be restored to its original position before a new password can be set.
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Error Reporting and Handling
6.
Error Reporting and Handling
Error Handling and Logging Error Messages and Beep Codes
This chapter defines the following error handling features:
6.1
Error Handling and Logging
This section defines how errors are handled by the system BIOS. In addition, error-logging techniques are described and beep codes for errors are defined.
6.1.1
Error Sources and Types
One of the major requirements of server management is to correctly and consistently handle system errors. System errors that can be enabled and disabled individually or as a group can be categorized as follows: PCI bus Memory single- and multi-bit errors Errors detected during POST, logged as POST errors The error list that would be logged is as follows:
Table 40. Event List
Event Name Processor thermal trip of last boot Memory channel A Multi-bit ECC error Memory channel A Single-bit ECC error Memory channel B Multi-bit ECC error Memory channel B Single-bit ECC error CMOS battery failure CMOS checksum error CMOS time not set Keyboard not found Memory size decrease Chassis intrusion detected Bad SPD tolerance Description Processor thermal trip happened on last boot. Multi-bit ECC error happened on DIMM channel A. Single-bit ECC error happened on DIMM channel A. Multi-bit ECC error happened on DIMM channel B. Single-bit ECC error happened on DIMM channel B. CMOS battery failure or CMOS clear jumper is set to clear CMOS. CMOS data crushed CMOS time is not set PS/2 KB is not found during POST Memory size is decreased compared with last boot Chassis is open Some fields of the DIMM SPD may not be supported, but could be tolerated by the Memory Reference Code. When Error Is Caught POST POST / Runtime POST / Runtime POST / Runtime POST / Runtime POST POST POST POST POST POST POST
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PCI PERR error PCI SERR error
PERR error happens on PCI bus SERR error happens on PCI bus
POST / Runtime POST / Runtime
6.1.2
Error Logging via SMI Handler
The SMI handler is used to handle and log system level events. The SMI handler pre-processes all system errors, even those that are normally considered to generate an NMI. The SMI handler logs the event to NVRAM. For example, the BIOS programs the hardware to generate a SMI on a single-bit memory error and logs the error in the NVRAM in terms of a SMBIOS Type 15. After the BIOS finishes logging the error it will assert the NMI if needed. 6.1.2.1 PCI Bus Error
The PCI bus defines two error pins, PERR# and SERR#. These are used for reporting PCI parity errors and system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#. All other PCI-related errors are reported by SERR#. All PCI-to-PCI bridges are configured so that they generate SERR# on the primary interface whenever there is SERR# on the secondary side. 6.1.2.2 PCI Express* Errors
Fatal and critical PCI Express* errors are logged as PCI system errors and are promoted to an NMI. All non-critical PCI Express errors are logged as PCI parity errors. 6.1.2.3 Memory Errors
The hardware is programmed to generate an SMI on correctable data errors in the memory array. The SMI handler records the error to the NVRAM. The uncorrectable errors may have corrupted the contents of SMRAM. The SMI handler will log the error to the NVRAM if the SMRAM contents are still valid.
6.1.3
SMBIOS Type 15
Errors are logged to the NVRAM in terms of the SMBIOS Type 15 (System Event Log). Please refer to the SMBIOS Specification, version 2.4 for more detail information. The format of the records is also defined in the following section.
6.1.4
Logging Format Conventions
The BIOS logs an error into the NVRAM area with the following record format, which is also defined in the SMBIOS Specification, version 2.3.4.
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Table 41. Logging Format Conventions
Offset 00h 01h Name EventType Length Length Byte Byte Description Specifies the "Type" of event noted in an event-log entry as defined in table. Specifies the byte length of the event record, including the record's Type and Length fields. Indicates the time when error is logged.
02h 03h 04h 05h 06h 07h 08h 0Ch
Year Month Day Hour Minute Second EventData1 EventData2
Byte Byte Byte Byte Byte Byte DWORD DWORD
EFI_STATUS_CODE_TYPE EFI_STATUS_CODE_VALUE
Table 42. Event Type Definition Table
Value 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh Reserved Single-bit ECC memory error Multi-bit ECC memory error Parity memory error Bus time-out I/O Channel Check Software NMI POST Memory Resize POST Error PCI Parity Error PCI System Error CPU Failure EISA FailSafe Timer time-out Correctable memory log disabled Logging disabled for a specific Event Type - too many errors of the same type received in a short amount of time Reserved System Limit Exceeded (e.g. voltage or temperature threshold exceeded) Asynchronous hardware timer expired and issued a system reset System configuration information Hard-disk information System reconfigured Uncorrectable CPU-complex error Log Area Reset/Cleared System boot. If implemented, this log entry is guaranteed to be the first one written on any system boot. Description N Y Y N N N N N Y Y Y N N N N Used by this platform (Y/N)
0Fh 10h 11h 12h 13h 14h 15h 16h 17h
N Y N N N N N Y N
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18h-7Fh 80h-FEh FFh
Unused, available for assignment by SMBIOS Specification Version 2.3.4. Available for system- and OEM-specific assignments End-of-log. When an application searches through the event-log records, the end of the log is identified when a log record with this type is found.
N Y Y
For more information about the EFI_STATUS_CODE_TYPE and EFI_STATUS_CODE_VALUE definitions, refer to "Intel Platform Innovation Framework for EFI Status Codes Specification", version 0.92. The errors are also displayed on the BIOS Setup screen under Server Management / View EventLog menu in the following format: EventName (times) Time of Occurrence
EventName is the same as that shown in the Table 58. It is followed by the number of occurrences of the same event. The `Time of Occurrence' is the last time the event occurred.
6.2
Error Messages and Error Codes
The system BIOS displays error messages on the video screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the video monitor.
6.2.1
Diagnostic LEDs
During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS will display the POST code on the POST code diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the diagnostic LEDs can be used to identify the last POST process to be executed. Each POST code is represented by a combination of colors from the four LEDs. The LEDs are capable of displaying three colors: green, red, and amber. The POST codes are divided into an upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red LED and each bit in the lower nibble is represented by a green LED. If both bits are set in the upper and lower nibbles then both red and green LEDs are lit, resulting in an amber color. If both bits are clear, then the LED is off. In the below example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Red bits = 1010b = Ah Green bits = 1100b = Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated to be ACh.
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Table 43. POST Progress Code LED Example
8h LEDs ACh Result Red 1 Amber MSB 1 Green 0 Green Red 1 4h Green 1 Red Red 0 2h Green 0 Off LSB Red 0 1h Green
USB Port
USB Port
Diagnostic LEDs
Back edge of baseboard
MSB LSB
Figure 6. Location of Diagnostic LEDs on Server Board
6.2.2
POST Code Checkpoints
Table 44. POST Code Checkpoints
Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB Host Processor Checkpoint 0x10h 0x11h 0x12h 0x13h Chipset 0x21h Memory 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h 0x28h PCI Bus 0x50h OFF R OFF R Enumerating PCI busses OFF OFF OFF OFF OFF OFF G OFF OFF G G G G OFF A A R R A A R OFF G OFF G OFF G OFF OFF OFF R G OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF G G R A R A
Description
Power-on initialization of the host processor (bootstrap processor) Host processor cache initialization (including AP) Starting application processor initialization SMM initialization Initializing a chipset component Reading configuration data from memory (SPD on DIMM) Detecting presence of memory Programming timing parameters in the memory controller Configuring memory parameters in the memory controller Optimizing memory controller settings Initializing memory, such as ECC init Testing memory
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Checkpoint 0x51h 0x52h 0x53h 0x54h 0x55h 0x56h 0x57h USB 0x58h 0x59h 0x5Ah 0x5Bh SMBUS 0x5Ch 0x5Dh Local Console 0x70h 0x71h 0x72h 0x78h 0x79h 0x7Ah 0x90h 0x91h 0x92h 0x93h 0x94h 0x95h 0x98h 0x99h 0x9Ah 0x9Bh Fixed Media 0xB0h 0xB1h 0xB2h 0xB3h
Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB OFF R OFF A OFF OFF OFF OFF OFF OFF G G G G G G OFF OFF OFF G G G R R R R R R A A A A R R R R R R A A A A R R R R A A R R R R R R OFF OFF OFF OFF G G OFF OFF OFF OFF OFF OFF OFF OFF G G OFF OFF G G OFF OFF G G OFF OFF R R A R R A OFF OFF G G OFF OFF OFF OFF G G R R A A R A R A R A R A R A R A R A R R A R R A R A R A R A R A R A R A
Description
Allocating resources to PCI busses Hot Plug PCI controller initialization Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Resetting USB bus Reserved for USB devices Begin PATA / SATA bus initialization Reserved for ATA Resetting SMBUS Reserved for SMBUS Resetting the video controller (VGA) Disabling the video controller (VGA) Enabling the video controller (VGA) Resetting the console controller Disabling the console controller Enabling the console controller Resetting the keyboard Disabling the keyboard Resetting the keyboard Enabling the keyboard Clearing keyboard input buffer Instructing keyboard controller to run Self Test (PS2 only) Resetting the mouse Detecting the mouse Detecting the presence of mouse Enabling the mouse Resetting fixed media device Disabling fixed media device Detecting presence of a fixed media device (IDE hard drive detection, etc.) Enabling / configuring a fixed media device
ATA / ATAPI / SATA
Remote Console
Keyboard (PS2 or USB)
Mouse (PS2 or USB)
Removable Media
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Checkpoint 0xB8h 0xB9h 0xBAh 0xBCh 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0XDA 0xDB 0xDC 0xDE 0xDF 0xE0h 0xE1h 0xE2h 0xE3h 0xE4h 0xE5h 0xE6h 0xEBh 0xECh DXE Drivers 0xE7h 0xE8h 0xE9h 0xEAh 0xEEh 0xEFh 0xF4h 0xF5h
Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB A OFF R R A A A R R R R R R R R A A A A A A A R R R R R R R A R R A A A A A R R OFF OFF G R R R R A A A A R R R R A A A R R R R A A A R A A R R R A A A A R A R OFF OFF G G OFF OFF G G OFF OFF G G OFF G G R R A A R R A A A A R R A A A R R A R R R A R A R A R A R A R A R R A OFF G OFF G OFF G OFF G OFF G OFF G OFF OFF G R A
Description
Resetting removable media device Disabling removable media device Detecting presence of a removable media device (IDE CDROM detection, etc.) Enabling / configuring a removable media device Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Trying boot device selection Started dispatching an PEIM Completed dispatching an PEIM Initial memory found, configured, and installed correctly Reserved for initialization module use (PEIM) Entered EFI driver execution phase (DXE) Reserved for DXE core use Started connecting drivers Started dispatching a driver Completed dispatching a driver Waiting for user input Checking password Entering BIOS setup Flash Update Calling Int 19. One beep unless silent boot is enabled. Reserved for DXE Drivers use Entering Sleep state Exiting Sleep state
Boot Device Selection
Pre-EFI Initialization (PEI) Core
Driver eXecution Environment (DXE) Core
Runtime Phase / EFI Operating System Boot
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Checkpoint 0xF8h 0xF9h 0xFAh
Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB A A A R R R R R A R A R
Description
Operating system has requested EFI to close boot services (ExitBootServices ( ) has been called) Operating system has switched to virtual address mode (SetVirtualAddressMap ( ) has been called) Operating system has requested the system to reset (ResetSystem () has been called) Crisis recovery has been initiated because of a user request Crisis recovery has been initiated by software (corrupt flash) Loading crisis recovery capsule Handing off control to the crisis recovery capsule Unable to complete crisis recovery.
Pre-EFI Initialization Module (PEIM) / Recovery 0x30h 0x31h 0x34h 0x35h 0x3Fh OFF OFF OFF OFF G OFF OFF G G G R R R R A R A R A A
6.2.3
POST Error Messages and Handling
Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs. The Response column in the following table is divided into two types: Pause: The message is displayed in the Error Manager screen, an error may be logged to the NVRAM, and user input is required to continue. The user can take immediate corrective action or choose to continue booting. Halt: The message is displayed in the Error Manager screen, an error is logged to the NVRAM, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.
*
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Table 45. POST Error Messages and Handling
Error Code Error Message CMOS date / time not set Configuration cleared by jumper Configuration default loaded Password check failed PCI resource conflict Insufficient memory to shadow PCI ROM Processor thermal trip error on last boot Response Pause Pause Pause Halt Pause Pause Pause Log Error Y Y N N N N Y
6.2.4
POST Error Beep Codes
The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users of error conditions. The beep code is followed by a user visible code on the POST Progress LEDs.
Table 46. POST Error Beep Codes
Beeps 3 Error Message Memory error POST Progress Code Description System halted because a fatal error related to the memory was detected.
6.2.5
POST Error Pause Option
In the event of POST error(s) that are listed as "Pause", the BIOS will enter the error manager and wait for the user to press an appropriate key before booting the operating system or entering BIOS Setup. The user can override this option by setting "POST Error Pause" to "disabled" in the BIOS Setup main menu page. If the "POST Error Pause" option is set to "disabled", the system will boot the operating system without user intervention. The default value is set to "enabled".
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7.1
Connectors and Jumper Blocks
Power Connectors
The power supply connection is supplied to the system through the 18-pin connector. The following table defines the pin-outs of the connector.
Table 47. Power Connector Pin-out (J3K1)
Pin 1* 2 3* 4* 5 6 7 8 9 Signal +3.3VDC 3.3V RS COM COM COM RS +5VDC 5V RS 5 VSB COM COM +12V1 +12V2 18 AWG Color Orange Orange (24AWG) Black Black Black (24AWG) Red Red (24AWG) Purple Black Black Yellow Yellow Pin 10 11 12 13 14 15 16 17 18 Signal +3.3VDC -12VDC COM PSON# +5VDC +12V1 COM COM +12V3 18 AWG Color Orange Blue Black Green Red Yellow Black Black Yellow
7.2
I2C Header
Table 48. HSBP Header Pin-out (J1C1)
Pin 1 2 3 4 SMB_DATA_5V_BP GND SMB_CLK_5V_BP GND
Signal Name Data Line GROUND Clock Line GROUND
Description
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7.3
Front Panel Connector
A standard SSI 34-pin header is provided to support a system front panel. The header contains reset, NMI, power control buttons, and LED indicators. The following table details the pin-out of this header.
Table 49. Front Panel 14-pin Header Pin-out (J4k2)
Signal Name Power LED Anode Power LED Cathode HDD Activity LED Anode HDD Activity LED Cathode Power Switch Power Switch(GND) Key Pin 1 3 5 7 9 11 13 Signal Name NIC1 Activity LED Anode NIC1 Activity LED Cathode NIC2 Activity LED Anode NIC2 Activity LED Cathode Reset Switch Reset Switch(GND) NC Pin 2 4 6 8 10 12 14
Note: NC (No Connect)
7.4
7.4.1
I/O Connectors
VGA Connector
The following table details the pin-out of the VGA connector. This connector is combined with the COM1 connector.
Table 50. VGA Connector Pin-out (J3A1)
Signal Name RED GREEN BLUE NC GND GND GND GND Note: NC (No Connect) Pin B1 B2 B3 B4 B5 B6 B7 B8 Signal Name Fused VCC (+5V) GND NC DDCDAT HSY VSY DDCCLK Pin B9 B10 B11 B12 B13 B14 B15
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7.4.2
NIC Connectors
The Intel(R) Entry Server Board SE7230CA1-E supports two NIC RJ-45 connectors. The following tables detail the pin-out of the connector.
Table 51. NIC1-Intel(R) 82573E (10/100/1000) Connector Pin-out (JA5A1)
Signal Name P2V5_NIC1 NIC1_MDI0_DP NIC1_MDI0_DN NIC1_MDI1_DP NIC1_MDI1_DN NIC1_MDI2_DP NIC1_MDI2_DN Pin 9 10 11 12 13 14 15 Signal Name NIC1_MDI3_DP NIC1_MDI3_DN GND NIC1_LINK_1_N P3V3_AUX NIC1_LINK_0_N NIC1_LINK_2_N Pin 16 17 18 19 20 21 22
Table 52. NIC2- Intel(R) 82541PI (10/100/1000) Connector Pin-out (JA4A1)
Signal Name P1V8_NIC_RC NIC2_MDI2_DN NIC2_MDI2_DP NIC2_MDI1_DP NIC2_MDI1_DN P1V8_NIC_RC P1V8_NIC_RC NIC2_MDI3_DP Pin 1 2 3 4 5 6 7 8 Signal Name NIC2_MDI3_DN NIC2_MDI0_DN NIC2_MDI0_DP P1V8_NIC_RC NIC2_LINK1000_N NIC2_LINK100_N NIC2_ACT_LED_N NIC2_LINK_UP_N Pin 9 10 11 12 13 14 15 16
7.4.3
SATA Connectors
The Intel(R) ICH7R integrates a SATA controller with four SATA ports. The pin-out for these four connectors is listed below.
Table 53. SATA Connector Pin-out (J5C1, J5C2)
Pin 1 2 3 4 5 6 7 GND SATA0_TX_P SATA0_TX_N GND SATA0_RX_N SATA0_RX_P GND Signal Name
7.4.4
Serial Port Connectors
One serial port is provided on the Intel(R) Entry Server Board SE7230CA1-E. A standard, external DB9 serial connector is located on the back edge of the server board to supply a Serial A interface. This connector is combined with the VGA connector (J3A1). An internal 9-pin header supplies a Serial B interface.
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Table 54. External DB9 Serial A Port Pin-out (J3A1)
Signal Name DCD RXD TXD DTR GND Pin T1 T2 T3 T4 T5 Signal Name DSR RTS CTS RI Pin T6 T7 T8 T9
Table 55. Internal 9-pin Serial B Port Pin-out (J1C2)
Signal Name DCD DSR RX RTS TX Pin 1 2 3 4 5 Signal Name CTS DTR RI GND Pin 6 7 8 9
7.4.5
USB Connector
The following table provides the pin-out for the dual external USB connectors. This connector is combined with an RJ-45 (connected to NIC1 signals).
Table 56. USB Connectors Pin-out (JA5A1)
Pin U1 U2 U3 U4 U5 U6 U7 U8 P5V_USB_BP_MJ USB_BACK5_R_DN USB_BACK5_R_DP GND P5V_USB_BP_MJ USB_BACK4_R_DN USB_BACK4_R_DP GND Signal Name
A header on the server board provides an option to support two additional USB ports. The pinout of the header is detailed in the following table.
Table 57. Optional USB Connection Header Pin-out (J9F2)
Signal Name NC GND USB_FRONT1_INDUCTOR_DP USB_FRONT1_INDUCTOR_DN USB_FNT_PWR (Fused VCC, +5V /w over current monitor of both port 1) Pin 1 3 5 7 9 Signal Name Key GND USB_FRONT2_INDUCTOR_DP USB_FRONT2_INDUCTOR_DN USB_FNT_PWR (Fused VCC, +5V /w over current monitor of both port 1) Pin 2 4 6 8 10
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7.5
Fan Headers
There are two general-purpose (system) fan headers (J3K2, J4K1). These fan headers have the same pin-out and are detailed below.
Table 58. Four-pin Fan Headers Pin-out (J3K2, J4K1)
Pin 1 2 3 4 Signal Name Ground Fan Power Fan Tach PWM Type Power Power Out Control Description GROUND is the power supply ground Fan Power +12VDC FAN_TACH signal is connected to the Heceta* to monitor the fan speed. Pulse Width Modulation - Fan speed Control signal
7.6
7.6.1
Miscellaneous Headers and Connectors
Chassis Intrusion Header
A 1x2 pin header (J3B2) is used in the chassis to support a chassis intrusion switch. The pin-out definition for this header is found in the following table.
Table 59. Intrusion Cable Connector (J3B2) Pin-out
Pin 1 2 Signal Name FP_INTRUDER_HDR_P1(Power) FP_INTRUDER_HDR_N
7.6.2
Back Panel I/O Connectors
Figure 7. Back Panel I/O Connections (not to scale)
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7.6.3 POST Code LEDs
Four POST code LEDs display POST code progression activities using hexadecimal format, read from the least significant bit to the most significant bit.
7.7
Jumper Blocks
This section describes configuration jumper options on the Intel(R) Entry Server Board SE7230CA1-E.
7.7.1
Clear CMOS and System Maintenance Mode Jumpers
Both the CMOS Clear and the system maintenance mode jumpers consist of 3-pin headers (CMOS Clear = J3B1, Config Mode = J1A3) located just beside the Front panel and SATA 1 connectors. The Intel(R) Entry Server Board SE7230CA1-E provides two 3-pin jumper blocks that are used to perform clearing of NVRAM and system maintenance mode options. The factory defaults are set to Normal mode for each function. The following tables describe each jumper option.
Table 60. System Maintenance Mode (J1A3)
Name Normal
Pin - Pin 1-2
Function Normal operation
Description Allows normal system operation with correct BIOS settings. System will POST normally. Maintenance mode overrides incorrect BIOS settings which would otherwise prohibit normal POST with safe settings for specific hardware configuration. Used to recover from a corrupted BIOS.
Config (Maintenance)
2-3
Machine Config Mode
Recovery boot
Off
BIOS Recovery Mode
Table 61. Clear CMOS Jumper Options (J3B2)
Name Normal Pin - Pin 1-2 Function Normal operation Description Jumper in normal position allows system to successfully POST and boot to operating system environment. BIOS settings are maintained intact. Jumper in CLEAR position initiates clear of NVRAM following POST. System message confirms CMOS clear operation successful. This setting enforces default BIOS settings, which can be changed by entering setup via F2, then exiting setup via F10 and saving changes.
CMOS Clear
2-3
Clears CMOS (NVRAM)
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8.
Absolute Maximum Ratings
Operating the board at conditions beyond those shown in the following table may cause permanent damage to the system. The table is provided for stress testing purposes only. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
Table 62. Absolute Maximum Ratings
5 C to 50 C 1 -55 C to +150 C -0.3 V to Vdd + 0.3V 2 -0.3 V to 3.63 V -0.3 V to 5.5 V
Operating Temperature Storage Temperature Voltage on any signal with respect to ground 3.3 V Supply Voltage with Respect to ground 5 V Supply Voltage with Respect to ground Notes: 1. 2.
Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature. VDD means supply voltage for the device
8.1
Mean Time Between Failures (MTBF) Test Results
This section provides results of MTBF testing conducted by an Intel testing facility. MTBF is a standard measure for the reliability and performance of the board under extreme working conditions. For the Intel(R) Entry Server Board SE7230CA1-E, MTBF was measured at 40 degrees Centigrade.
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9.
9.1
Design and Environmental Specifications
Power Budget
The following table shows the power consumed on each supply line for the Intel(R) Entry Server Board SE7230CA1-E that is configured with one processor (130W max). This configuration includes four 1-GB DDR2 DIMMs stacked burst at 90% max. The numbers provided in the table should be used for reference purposes only. Different hardware configurations will produce different numbers. The numbers in the table reflect a common usage model operating at higher than average stress levels.
Table 63. The Board Power Budget
Watts Functional Unit Server Board Input Totals Server Board Discrete Totals Server Board Converters Server Board Config Totals System Components System Totals 3.3V / 5V Combined Power Power Supply Requirements - 1U 300W 350W peak 3.3V/5V Combined Power 100W 1Amin 1Amin 2Amin 2Amin 0Amin 1Amin 14A 18A Max 12V+ 12V VRM 0.5A 2A 50% Efficiency Utilization Power 260W 45W 40W 175.8W 29W 291W 3.3V 2.9 2.9 0.00 0.00 0.00 2.9 Power Supply Rail Voltages AMPS 5.V 13.9 0.5 13.4 0.00 2.8 15.2 12.V 2.8 0.00 0.00 2.8 3.6 4.7 12V VRM 12.2 0.00 12.2 0.00 0.00 12.2 -12v 0.05 0.00 0.00 0.05 0.00 0.05 5VSB 1.54 0.04 1.5 0.00 0.00 1.54 Amps Amps Amps Amps Amps Amps Units
9.2
9.2.1
Product Regulatory Compliance
Product Safety Compliance
(R)
The Intel Entry Server Board SE7230CA1-E complies with the following safety requirements: UL60950 - CSA 60950(USA / Canada) EN60950 (Europe) IEC60950 (International) CB Certificate and Report, IEC60950 (report to include all country national deviations)
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CE - Low Voltage Directive 73/23/EEE (Europe)
9.2.2
Product EMC Compliance - Class A Compliance
Note: Legally the product is required to comply with Class A emission requirements as it is intended for a commercial type market place. Intel targets 10db margin to Class A Limits The Intel(R) Entry Server Board SE7230CA1-E has been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed in a compatible Intel(R) host system. For information on compatible host system(s), refer to Intel's Server Builder Web site or contact your local Intel representative. FCC /ICES-003 - Emissions (USA/Canada) Verification CISPR 22 - Emissions (International) EN55022 - Emissions (Europe) CE - EMC Directive 89/336/EEC (Europe) AS/NZS 3548 Emissions (Australia / New Zealand)
9.2.3
Certifications / Registrations / Declarations
UL Certification (US/Canada) CB Certification (International) CE Declaration of Conformity (CENELEC Europe) FCC/ICES-003 Class A Attestation (USA/Canada) C-Tick Declaration of Conformity (Australia) MED Declaration of Conformity (New Zealand)
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9.2.4
Product Regulatory Compliance Markings
This product is marked with the following Product Certification Markings:
Table 64. Product Certification Markings
Regulatory Compliance UL Mark
Region USA/Canada
Marking
E139761 CE Mark Europe
Canada EMC Mark C-Tick Mark
Canada Australia
CANADA ICES-003 CLASS A
Country of Origin
Exporting Requirements
MADE IN xxxxx (provided by label not silkscreen)
Model Designation
Regulatory Identification
Board PB Number will be used for the Model number
PB Free Marking
Environmental Requirements
9.3
9.3.1
Electromagnetic Compatibility Notices
Industry Canada (ICES-003)
Cet appareil numerique respecte les limites bruits radioelectriques applicables aux appareils numeriques de Classe A prescrites dans la norme sur le materiel brouilleur: "Apparelis Numeriques", NMB-003 edictee par le Ministre Canadian des Communications. This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled: Digital Apparatus, ICES-003 of the Canadian Department of Communications.
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Intel(R) Entry Server Board SE7230CA1-E TPS
9.3.2
Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.
9.3.3
Australia / New Zealand
This product has been tested and complies with AS/NZS 3548. The product has been marked with the C-Tick mark to illustrate compliance.
9.4
Restriction of Hazardous Substances (RoHS)
Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an approved/pending RoHS exemption applies. Note: RoHS implementing details are not fully defined and may change. Threshold limits and banned substances are noted below. Quantity limit of 0.1% by mass (1000 PPM) for: o Lead o Mercury o Hexavalent Chromium o Polybrominated Biphenyls Dipheny Ethers (PBDE) Quantity limit of 0.01% by mass (100 PPM) for: o Cadmium
9.5
Calculated Mean Time Between Failures (MTBF)
The MTBF (Mean Time Between Failures) for the Intel(R) Entry Server Board SE7230CA1-E as configured from the factory is shown in the table below.
Table 65. MTBF Data
Product Code Intel(R) Entry Server Board SE7230CA1-E Operating Temperature 40 degrees C
9.6
Mechanical Specifications
The following figure shows a mechanical drawing of the Intel(R) Entry Server Board SE7230CA1E.
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Intel(R) Entry Server Board SE7230CA1-E TPS
Design and Environmental Specifications
Figure 8. Intel(R) Entry Server Board SE7230CA1-E Mechanical Drawing
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Hardware Monitoring
Intel(R) Entry Server Board SE7230CA1-E TPS
10. Hardware Monitoring
10.1 Monitored Components
The Intel(R) Entry Server Board SE7230CA1-E has an integrated Heceta chip that is responsible for hardware monitoring. The Heceta chip provides basic server hardware monitoring which alerts a system administrator if a hardware problem occurs on the board. The SMsC* LP47M182NR has implemented some fan speed control/monitor pins. Below is a table of monitored headers and sensors on the board.
Table 66. Monitored Components
Item VCCP (PIN #23) P12V (PIN #21) 2.5V (PIN #22) P5V (PIN #20) Fan Speed PWM1 (PIN #24) PWM2 (PIN #10) PWM3 (PIN #13) Description Monitors processor voltage Monitors +12Vin for system +12V supply Monitors 1.5V Core power Monitors +5V N/A Controls system fan 1 (J3K2) Controls system fan 2 (J4K1) Heceta* Heceta* Heceta* Heceta* Heceta* Heceta* Heceta* Heceta* Heceta* Heceta* Heceta*
Voltage
TACH1 (PIN #11) N/A TACH2 (PIN #12) Monitors system fan 1 (J3K2) TACH3 (PIN #9) Temperature H_THEMP_DA/C Monitors system fan 2 (J4K1) Monitors processor temperature
10.1.1
Fan Speed Control
Figure 9. Fan Speed Control Block Diagram
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Hardware Monitoring
10.2
Chassis Intrusion
The Intel(R) Entry Server Board SE7230CA1-E supports a chassis security feature that detects if the chassis cover is removed. This security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion connector. When the chassis cover is removed, the mechanical switch is in the open position.
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Reference Documents
Glossary
This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., "82460GX") with alpha entries following (e.g., "AGP 4x"). Acronyms are then entered in their respective place, with non-acronyms following.
Term ACPI ANSI AP ASIC ASR BGA BIOS Byte CMOS DCD DMA DMTF ECC EMC EPS ESCD FDC FIFO FRU GB GPIO GUID Hz HDG I2C IA ICMB IERR IMB IP IRQ ITP KB KCS LAN LBA LCD LPC Definition Advanced Configuration and Power Interface American National Standards Institute Application Processor Application Specific Integrated Circuit Asynchronous Reset Ball-grid Array Basic input/output system 8-bit quantity. In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. Data Carrier Detect Direct Memory Access Distributed management Task Force Error Correcting Code Electromagnetic Compatibility External Product Specification Extended System Configuration Data Floppy Disk Controller First-In, First-Out Field replaceable unit 1024 MB. General purpose I/O Globally Unique ID Hertz (1 cycle/second) Hardware Design Guide Inter-integrated circuit bus Intel(R) architecture Intelligent Chassis Management Bus Internal error Inter Module Bus Internet Protocol Interrupt Request In-target probe 1024 bytes Keyboard Controller Style Local area network Logical Block Address Liquid crystal display Low pin count
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Term LSB MB MBE Ms MSB MTBF Mux NIC NMI OEM Ohm PBGA PERR PIO PMB PMC PME PnP POST PWM RAIDIOS RAM RI RISC RMCP ROM RTC SBE SCI SDR SDRAM SEL SERIRQ SERR SM SMI SMM SMS SNMP SPD SSI TPS UART
Definition Least Significant Bit 1024 KB Multi-Bit Error milliseconds Most Significant Bit Mean Time Between Failures multiplexor Network Interface Card Non-maskable Interrupt Original equipment manufacturer Unit of electrical resistance Pin Ball Grid Array Parity Error Programmable I/O Private Management Bus Platform Management Controller Power Management Event Plug and Play Power-on Self Test Pulse-Width Modulator RAID I/O Steering Random Access Memory Ring Indicate Reduced instruction set computing Remote Management Control Protocol Read Only Memory Real Time Clock Single-Bit Error System Configuration Interrupt Sensor Data Record Synchronous Dynamic RAM System event log Serialized Interrupt Requests System Error Server Management Server management interrupt. SMI is the highest priority nonmaskable interrupt System Management Mode System Management Software Simple Network Management Protocol Serial Presence Detect Server Standards Infrastructure Technical Product Specification Universal asynchronous receiver and transmitter
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Reference Documents
Term USB VGA VID VRM Word ZCR
Definition Universal Serial Bus Video Graphic Adapter Voltage Identification Voltage Regulator Module 16-bit quantity Zero Channel RAID
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References
Advanced Configuration and Power Interface Specification, Revision 1.0b, February 1999, http://www.acpi.info/ Advanced Configuration and Power Interface Specification, Revision 2.0, July 2000, http://www.acpi.info/ Advanced Configuration and Power Interface Specification, Revision 3.0, , http://www.acpi.info/ BIOS Boot Specification Version 1.01. Compaq Computer Corporation, Phoenix Technologie Ltd., Intel Corporation. 1996, http://www.phoenix.com/resources/specsbbs101.pdf El Torito CD-ROM Boot Specification, Version 1.0, http://www.phoenix.com/resources/specs-cdrom.pdf Extensible Firmware Interface Reference Specification, Version 1.1, http://www.intel.com/technology/efi/index.htm Tiano EFI Shell EPS, Revision 0.10. Intel Corporation, 2002 EFI 1.1 Shell Commands Specification, v0.3, Available from: EFI1.1ShellCommands.pdf, EFI sample implementation, revision 1.10.14.62, http://developer.intel.com/technology/efi/main_sample.htm IA-32e BIOS Writer's Guide, Revision 0.5, Intel Corporation Platform Management FRU Information Storage Definition v1.0, http://developer.intel.com/design/servers/ipmi Hardware Design Guide for Microsoft Windows 2000 Server, Version 3.0, http://www.microsoft.com/whdc/system/platform/pcdesign/desguide/serverdg.mspx#ESB Application Note AP-485: Intel Processor Identification and the CPUID Function, http://www.intel.com/design/xeon/applnots/241618.htm Intelligent Platform Management Bus Specification, Version 1.0, http://developer.intel.com/design/servers/ipmi/spec.htm Intelligent Platform Management Interface Specification, Version 1.5, http://developer.intel.com/design/servers/ipmi/spec.htm Intelligent Platform Management Interface Specification, Version 2.0, http://developer.intel.com/design/servers/ipmi/spec.htm Multiprocessor Specification, Revision 1.4, May 1997 Microsoft Headless Design Guidelines, http://www.microsoft.com/HWDEV/PLATFORM/server/headless/default.asp PCI Local Bus Specification, Revision 3.0, http://www.pcisig.org/ PCI Local Bus Specification, Revision 2.2, http://www.pcisig.org/
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Reference Documents
PCI BIOS Specification, Revision 2.1, http://www.pcisig.org/ PCI to PCI Bridge Specification, Revision 1.1, http://www.pcisig.org/ PCI Express Base Specification, Revision 1.0a, http://www.pcisig.org/ PCI Hot-Plug Specification, Revision 1.1, http://www.pcisig.org/ PCI IRQ Routing Table Specification, Revision 1.0, Microsoft Corporation Plug and Play BIOS Specification, Revision 1.0a (relevant portions only), http://www.microsoft.com/whdc/system/pnppwr/pnp/default.mspx Sahalee Baseboard Management Controller Core External Product Specification for Silverwood Systems, Intel Corporation System Management BIOS Reference Specification, Version 2.4, http://www.dmtf.org/standards/smbios ACPI Static Resource Affinity Table, Version 1.2, http://www.microsoft.com/whdc/hwdev/platform/proc/SRAT.mspx SYSID BIOS Support Interface Requirement Specification, Version 1.2 Intel(R) Platform Innovation Framework for EFI Firmware Volume Specification, Revision 0.9, Intel Corporation, 2004, ftp://download.intel.com/technology/framework/docs/Fv.pdf Universal Host Controller Interface Design Guide, http://developer.intel.com/design/USB/UHCI11D.htm Universal Serial Bus Revision 1.1 Specification, http://www.usb.org/developers/docs Universal Serial Bus Revision 2.0 Specification, http://www.usb.org/developers/docs Wired For Management Baseline Specification, Revision 2.0, http://www.intel.com/labs/manage/wfm/wfmspecs.htm DMTF Systems Standard Groups Definition
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